Rapid design of high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel

This paper describes methods for the rapid design and VLSI implementation of two key components (the adaptive filter and Viterbi decoder) of the class-IV partial response maximum likelihood channel (PR-IV). These are implemented using parameterized modules, constructed from a synthesizable silicon architecture library containing core DSP and arithmetic functions. Design studies, based on a 0.35 micron 3.3 V standard cell CMOS process, indicate that worst case sampling rates of 180 mega-samples per second are achievable with a power consumption of 0.8 W and an area of 4.3 mm/sup 2/. Higher sampling rates can be obtained by operating a number of filter modules in parallel. This approach offers power saving advantages when compared with systems employing pipelined filters operating at the same speed.