Digit-serial reconfigurable FPGA logic block architecture

This paper presents a novel field-programmable gate array logic block architecture which incorporates support for digit-serial DSP architectures on a digit-wide basis, without diminishing the support for random and control logic applications. To efficiently realize a digit-serial DSP design on FPGA, one must create an FPGA architecture optimized for those types of systems. The key to the suitability of the FPGA for these applications is the fact that each of its basic blocks is capable of processing a digit size of up to 8 bits. A novel digit-serial FPGA logic block architecture has been proposed to satisfy the requirement of rapid prototyping and efficient implementation of digit-serial DSP applications. Digit-serial DSP designs using the digit-serial FPGA are compared to those implemented on a Xilinx FPGA chip. The results show that the normalized area of digit-serial circuits on the DS-FPGA is only 33/spl sim/54% of the number required on the Xilinx FPGA.