FPGA上的数字解调器匹配

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI:10.1109/SIPS.1998.715799

E. Boutillon, J. Danger, Leila Maria Garcia Fonseca, A. Garcia, L. González

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引用次数: 1

摘要

提出了一种基于FPGA设计的数字解调器。在介绍了解调算法之后，我们描述了它在可编程逻辑器件(ALTERA FLEX10K100)上的集成。我们专注于FPGA特性如何改变设计人员在设计流程各个层面的专业知识，从位级到算法级和方法学级。

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Digital demodulator matching on a FPGA

We present a digital demodulator based on a FPGA design. After the presentation of the demodulator algorithm, we describe its integration on a programmable logic device (ALTERA FLEX10K100). We focus on how the FPGA characteristics can change the expertise of the designer at all levels of the design flow, from bit level to algorithm level and methodology level.

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来源期刊

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

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