A uniform analysis method for DSP architectures and instruction sets with a comprehensive example

As digital signal processing finds broader areas of application, more processors are adapting to the need for DSP operations. MMX instructions have been added to the Pentium, high-performance RISC have done similar things for workstations, and microcontrollers are doing it for embedded applications. Digital signal processors too are changing as there are increased demands for higher performance. With new processors having such vastly different architectures and employing different processing strategies, it is increasingly difficult to make meaningful DSP performance comparisons between them. This paper reviews the normal representations or views of a processor: hardware architecture, programming model, instruction set architecture and benchmarks, and their role in DSP performance estimation in four critical areas. A uniform model is proposed for the first three views, which includes a new annotated form of programming model using signal-flow-graph-like techniques. Finally, one of the new types of processors, the Siemens TriCore Microcontroller-DSP, is analyzed to test and illustrate the new models and methodology.