1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)最新文献_第4页

A flexible approach and VLSI architecture for computing discrete time-frequency distribution 计算离散时频分布的灵活方法和VLSI架构

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715781

T. Le, T. Dombek, Jürgen Becker, Manfred Glesner

{"title":"A flexible approach and VLSI architecture for computing discrete time-frequency distribution","authors":"T. Le, T. Dombek, Jürgen Becker, Manfred Glesner","doi":"10.1109/SIPS.1998.715781","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715781","url":null,"abstract":"Time-frequency distribution (TFD) based on Cohen's class has significant potential for the analysis of a number of non-stationary signals, including speech, biomedical signals and machine vibration. The implementation of discrete signals has led to the definition of many different discrete TFD. The spectral decomposition of the kernel allows the computation of the generalized discrete-time TFD (GDTFD) as a weighted sum of spectrograms with orthonormal windows. The partial sum offers the user a vehicle to perform trade-off between exactness and computational requirement. We extend this idea by showing that the combination of incremental refinement and approximating structure along with the spectral decomposition-based GDTFD provides more flexibility and a variety of trade-offs between approximation quality and computational cost. The paper discusses aspects of a suitable VLSI architecture featuring modular structure, local connections and reconfigurable logic module for implementation. The result serves as a basis to design a programmable core for computing GDTFD within an integrated mechatronic system targeting fault detection.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125891389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A heterogeneous HW-SW architecture for hand-held multimedia terminals 面向手持多媒体终端的异构HW-SW架构

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715774

A. Nieuwland, P. Lippens

引用次数: 18

RNS scaling based on pipelined multipliers for prime moduli 基于素模管道乘法器的RNS缩放

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715808

A. García, A. Lloris

引用次数: 8

An enhanced template matching algorithm and its chip implementation 一种增强的模板匹配算法及其芯片实现

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715779

S. Seo, M. Sunwoo

引用次数: 1

A block-floating-point system for multiple datapath DSP 用于多数据路径DSP的块浮点系统

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715805

S. Kobayashi, G. Fettweis

引用次数: 11

A 1200 bits/s HSX speech coder for very-low-bit-rate communications 用于极低比特率通信的1200比特/秒HSX语音编码器

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715797

P. Gournay, F. Chartier

引用次数: 4

Multiport memory and floating point Cordic pipeline in Jacobium processing elements Jacobium处理元件中的多端口存储器和浮点Cordic管道

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715803

Alco Looye, G. Hekstra, E. Deprettere

{"title":"Multiport memory and floating point Cordic pipeline in Jacobium processing elements","authors":"Alco Looye, G. Hekstra, E. Deprettere","doi":"10.1109/SIPS.1998.715803","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715803","url":null,"abstract":"The Jacobium is a dataflow processor intended for high-speed execution of a set of algorithms that are akin to the so-called Jacobi method for reducing a symmetric matrix to diagonal form using Givens rotations. The design of this processor has been undertaken as one of two cases in a recently proposed method for the quantitative analysis of domain-specific dataflow architectures. The method presupposes that the exploration of the processor's design space starts out of a given architecture template whose free parameters are to be determined in such a way that the ultimate specification is in some sense optimal for a set of applications that are given from the outset. Two templates have been considered in the Jacobium case: one for the complete (multiple processor element) processor and one for a typical processor element (PE). A parametrized VHDL version of the latter has been designed as well. The architecture of such a typical PE is presented here. It is equipped with a deep floating point Cordic pipeline, on-chip multiport memory to buffer operands and results, and several high-speed communication buses for communication between processing elements and the host. This parametrized architecture serves two purposes: it can provide realistic estimates for the PE parameters at the level of the complete processor; and it can be used to validate the exploration results.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129402992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Implementation of a DSSS modem ASIC chip for wireless LAN 一种用于无线局域网的DSSS调制解调器ASIC芯片的实现

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715787

Hyunman Chang, M. Sunwoo

引用次数: 6

Differential Kalman filtering for tracking Rayleigh fading channels 基于差分卡尔曼滤波的瑞利衰落信道跟踪

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715800

Mohammad Javad Omidi, Saeed Gazor, P. G. Gulak, S. Pasupathy

引用次数: 5

A fixed-point multimedia DSP chip for portable multimedia services 一种用于便携式多媒体业务的定点多媒体DSP芯片

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715772

S. Ong, M. Sunwoo, M. Hong

引用次数: 6