An enhanced template matching algorithm and its chip implementation

Abstract

This paper presents an enhanced template matching algorithm and its chip implementation. The proposed algorithm called the enhanced moment preserving pattern matching (EMPPM) improves the noise margin by 22% compared with the previously proposed algorithm called the moment preserving pattern matching (MPPM) algorithm. In addition, the proposed architecture can reduce the gate count by more than 28% compared with the MPPM architecture. We have implemented behavior and structure models using VHDL and performed logic synthesis using the Synopsys/sup TM/ CAD tool. The actual chip has been implemented using the Samsung/sup TM/ 0.6 /spl mu/m SOG (sea-of-gate) cell library. The implemented chip consists of 35,827 gates, operates at 100 MHz and performs 16/spl times/16 template matching with a speed of 200 Mpixels/s.