A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs

Abstract

Driven by the rapid advances in semiconductor technology the number of functional units that can be implemented on a single chip is rapidly increasing. This raises the need for programmable but small processor cores to handle control of operation as well as communication and synchronization between the different functional modules on the chip. We have developed a soft core generator for highly parameterizable RISC-cores. The instruction word width can be arbitrarily chosen between 8 and 32 bits. Independent of this, the data-path width can be selected between 8 and 64 bits respectively. DSP-like performance can be achieved with the instantiation of a 64-bit (splittable-) MAC-unit in the data-path. The number of registers is arbitrarily scalable. The resulting cores are generated in RTL-VHDL and are fully synthesizable. Worst-case timing simulation shows 100 MHz achievable clock-speed using a 3LM 0.5 /spl mu/m standard-cell technology. The size of the synthesized cores ranges from 900 gates for a multi-cycle 8 bit core to 10k gates for a 5-stage pipelined 32 bit core with 8 registers. Interfaces and behavioral models are provided for instruction and data memories as well as a runnable VHDL testbench with basic test patterns. As a result, a 16 bit RISC core with instruction and data memories can be implemented on 1 mm/sup 2/ of silicon area in a 0.35 /spl mu/m technology.