2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)最新文献

An Approximate Adder Design Based on Inexact Full Adders 基于不精确全加法器的近似加法器设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651713

Wenqiang Yang, Lunyao Wang, Kailei Li

引用次数: 1

A Precise 3D Positioning Approach Based on UWB with Reduced Base Stations 一种基于超宽带减少基站的精确三维定位方法

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651683

Zhiqiang Xu, Zhu Liang, Ziheng Zhou, Zhenmin Li, Gaoming Du, Xiaolei Wang, Yuanyuan Song

引用次数: 4

Subcircuit Identification Method Based on Subgraph Isomorphism 基于子图同构的子电路识别方法

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651490

Guangxian Dong, Yalin Zheng, Shan He, Donghui Guo, Lin Li

引用次数: 0

Design of Combinational Digital Circuits Optimized with Ising Model and PSO Algorithm 用Ising模型和粒子群算法优化组合数字电路的设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651723

Ying Li, Penglei Zhao, Bingrui Guo, Chenhui Zhao, Xiaojie Liu, Shan He, Donghui Guo

{"title":"Design of Combinational Digital Circuits Optimized with Ising Model and PSO Algorithm","authors":"Ying Li, Penglei Zhao, Bingrui Guo, Chenhui Zhao, Xiaojie Liu, Shan He, Donghui Guo","doi":"10.1109/asid52932.2021.9651723","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651723","url":null,"abstract":"Evolutionary circuit is an important part of electronic design automation. It is a kind of automatic circuit design system by intelligent algorithm, widely used in robot controller design, circuit design and other fields. Compared with other intelligent algorithms, Particle Swarm Optimization (PSO) has better performance in the process of circuit evolution, but it has the disadvantage of falling into local optimum easily during evolution, resulting in meaningless increase of computing resources. This paper proposes a hybrid algorithm based on Ising model and PSO algorithm for optimizing combinational logic circuits. The Ising model is a kind of stochastic process model describing the material phase transition and has the property that it can accept a worse solution than the current one with a certain probability, which can increase the diversity of particles and avoid particles trapped in local optima point during the evolutionary process. Experimental results show that the hybrid algorithm has better performance in terms of computational complexity and circuit area.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design of A New Type of Regular Expression Matching Engine Based on FPGA 一种基于FPGA的新型正则表达式匹配引擎设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651676

Nan Jiang, Ping Lin, Yulong He, Zhuozhi Tan, Jin Hu

{"title":"Design of A New Type of Regular Expression Matching Engine Based on FPGA","authors":"Nan Jiang, Ping Lin, Yulong He, Zhuozhi Tan, Jin Hu","doi":"10.1109/asid52932.2021.9651676","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651676","url":null,"abstract":"In order to solve the problem that the computing power of processors in the post-Moore era cannot keep up with the speed of daily data generation, improve the ability of data retrieval and replacement, and ensure practicability, we learn from previous research and switch from traditional software to hardware to achieve regular matching. Based on the regular expression of the road characteristic, a regular matching hardware engine architecture is proposed and designed. Using RAM characteristics in this circuit, through different input configurations, there is no need to re-modify the circuit in the FPGA, so that it can achieve different pattern matching functions. It solves part of the generality problems caused by the diversity of modes, and satisfies common scenarios that require dynamic update of matching rules. And all matching processes are completed by only one basic core, saving a lot of logic resources. The processing speed is roughly 1 clock and 1 cycle to process 1 byte, which is close to the processing limit of digital circuits for single-byte data streams. Finally, the circuit is analyzed and compared with the circuit performance of typical research in the past, and the research work in the future is prospected.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130457378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design of a column-parallel SAR/SS two-step hybrid ADC for sensor arrays 用于传感器阵列的列并行SAR/SS两步混合ADC设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651680

Zheng Wang, Xu Liu, Peiyuan Wan, Zhijie Chen

引用次数: 1

A High-Speed Carry-Select Adder with Optimized Block Sizes 具有优化块大小的高速进位选择加法器

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651488

Ying-Yi Chu, Shao-Hui Shieh, Hai Feng, Hanyong Deng, M. Shiau, Der-Chen Huang

引用次数: 1

FPGA Implementation of Hardware Accelerator for Real-time Video Image Edge Detection 实时视频图像边缘检测硬件加速器的FPGA实现

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651710

Xiangxiang Wei, Gaoming Du, Xiaolei Wang, Hongfang Cao, Shijie Hu, Duoli Zhang, Zhenmin Li

{"title":"FPGA Implementation of Hardware Accelerator for Real-time Video Image Edge Detection","authors":"Xiangxiang Wei, Gaoming Du, Xiaolei Wang, Hongfang Cao, Shijie Hu, Duoli Zhang, Zhenmin Li","doi":"10.1109/asid52932.2021.9651710","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651710","url":null,"abstract":"Image edge is considered to be the most important attribute to provide valuable image perception information. At present, video image data is developing towards high resolution and high frame number. The image data processing capacity is huge, so the processing speed is very strict to meet the real-time performance of image data transmission. In this context, we present a method to accelerate the real-time video image edge detection. FPGA is used as the development platform. The real-time edge detection algorithm of image data with 1280x720 resolution and 30 frame/s, combined with median filter, Sobel edge detection algorithm and corrosion expansion algorithm, makes the running time of image processing module shorter. The color image of the video image collected by camera is processed. The HDMI interface shows that the scheme has achieved ideal results in the FPGA hardware platform simulation model, greatly improves the efficiency of the algorithm, and provides a guarantee for the speed and stability of the real-time image processing system.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129385641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design of a Low-Voltage Instrumentation Amplifier at 1.2 V 1.2 V低压仪表放大器的设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651684

Jeni Liao, Jianxiong Yang, Kangling, Minjuan Zheng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu

引用次数: 1

Cervical Lesions Classification Based on Pre-trained MobileNet Model 基于预训练MobileNet模型的宫颈病变分类

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651726

Tianxiang Xu, Ping Li, Xiao-xi Wang

引用次数: 0