2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)最新文献_第5页

Hardware Design of SHA-3 for PQC Classic McEliece PQC经典mcelece的SHA-3硬件设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651693

Xin Zhou, Liji Wu, Xiangmin Zhang

{"title":"Hardware Design of SHA-3 for PQC Classic McEliece","authors":"Xin Zhou, Liji Wu, Xiangmin Zhang","doi":"10.1109/asid52932.2021.9651693","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651693","url":null,"abstract":"As the computing power of quantum computers continues to improve, the security of the mathematical problems on current-used cryptographic algorithm are facing more and more serious challenge. It is necessary to formulate the standard of post-quantum cryptographic algorithm. Classic McEliece is one of the 7 candidates entering the Round 3 of NIST PQC contest. In the decryption module of Classic McEliece, H module uses the SHA-3 algorithm. As a new generation of hash algorithm, SHA-3 algorithm uses the Keccak sponge function, which has the advantages of higher speed, higher throughput and stronger security. Keccak truly realizes the processing of input information of any length, and can also generate hash values of any length. In the future, SHA-3 will be applied to more fields, so the high-performance and flexible implementation of the SHA-3 is especially important. This paper analyzed the four SHA-3 algorithms, and integrated the four algorithm standards into one implementation for Classic McEliece. The Xilinx Zynq-7000 series FPGA is chosen as the implementation and verification platform, and the performance are compared with the algorithm implementation of Keccak official team.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120844742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Parallel Concatenated Code Combining Polar Code and LDPC Code on AWGN Channel AWGN信道上极性码与LDPC码的并行级联码

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651728

Luyao Ma, Lijun Zhang

引用次数: 0

Energy-Efficient Deep Neural Networks Implementation on a Scalable Heterogeneous FPGA Cluster 基于可扩展异构FPGA集群的节能深度神经网络实现

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651719

Yanbu Hu, C. Shao, Huiyun Li

{"title":"Energy-Efficient Deep Neural Networks Implementation on a Scalable Heterogeneous FPGA Cluster","authors":"Yanbu Hu, C. Shao, Huiyun Li","doi":"10.1109/asid52932.2021.9651719","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651719","url":null,"abstract":"In recent years, with the rapid development of DNN, the algorithm complexity in a series of fields such as computer vision and natural language processing is increasing rapidly. FPGA-based DNN accelerators have demonstrated superior flexibility and performance, with higher energy efficiency compared to high-performance devices such as GPU. However, the computing resources of a single FPGA are limited and it is difficult to flexibly meet the requirements of high throughput and high energy efficiency of different computing scales. Therefore, this paper proposes a DNN implementation method based on the scalable heterogeneous FPGA cluster to adapt to different tasks and achieve high throughput and energy efficiency. Firstly, the method divides a single enormous task into multiple modules and running each module on different FPGA as the pipeline structure between multiple boards. Secondly, a task deployment method based on dichotomy is proposed to maximize the balance of task execution time of different pipeline stages to improve throughput and energy efficiency. Thirdly, optimize DNN computing module according to the relationship between computing power and bandwidth, and improve energy efficiency by reducing waste of ineffective resources and improving resource utilization. The experiment results on Alexnet and VGG-16 demonstrate that we use Zynq 7035 cluster can at most achieves ×25.23 energy efficiency of optimized AMD AIO processor. Compared with previous works of single FPGA and FPGA cluster, the energy efficiency is improved by 59.5% and 18.8%, respectively.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125572861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651725

引用次数: 0

Moving Object Detection and Marking Based on Frame Difference and Train Algorithm for Teaching Video 基于帧差和训练算法的教学视频运动目标检测与标记

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651485

Zhenyu Wang, Junping Wang, Nan Wang

引用次数: 1

Secure Turbo-Polar Codes Information Transmission on Wireless Channel 无线信道上Turbo-Polar码信息的安全传输

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651705

Guang-Chong Zhu, Deyuan Chen, Can Zhang, Yongzhi Qi

引用次数: 0

Designs of 16-to-24-GHz Inductor-Capacitor Digitally-Controlled Oscillators in 40-nm CMOS 40纳米CMOS 16 ~ 24 ghz电感-电容数字控制振荡器的设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651699

Yanian Shao, Xuefei Bai, Zhe Yang

引用次数: 0

A Novel Active Inductor with Almost Simultaneously Constant L and Peak Q at Different Frequencies and Independent Q Tunability 一种新颖的有源电感，在不同频率下几乎同时保持恒定的L和峰值Q，并且Q可独立调谐

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651674

Yamei Xu, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yan Liang, Ziteng Cai

{"title":"A Novel Active Inductor with Almost Simultaneously Constant L and Peak Q at Different Frequencies and Independent Q Tunability","authors":"Yamei Xu, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yan Liang, Ziteng Cai","doi":"10.1109/asid52932.2021.9651674","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651674","url":null,"abstract":"A novel Active Inductor (AI) is presented that its inductance values L and the peak values of quality factor Q can be kept almost constant at different frequencies, and the Q factor can be independently tuned with respect to the inductance value L. The external voltage tuning terminal of the positive transconductor in the feedback loop of positive and negative transconductors building block is configured to compensate for the variation of inductance with frequency. And the external voltages of two building blocks, namely the multi-regulated cascode structure circuit and RC feedback network are jointly tuned to compensate for the variation of Q value with frequency. In addition, the variable capacitance in the RC feedback network is employed to tune the Q factor without affecting the inductance value, thus the independent tuning of the Q with respect to the inductance value is realized. Based on TSMC 0.18ȝm CMOS process, the novel AI is verified by Advanced Design System (ADS). The results show that under the frequencies of 0.75GHz, 1.85GHz, 3.00GHz, 4.10GHz, the novel AI achieves the peak Q values of 999, 1003, 999 and 1001 respectively with the peak Q variation of only 0.40%. At the same time, the corresponding inductance values are 316.0nH, 310.2nH, 309.6nH and 303.1nH respectively with the inductance variation of only 4.17%. Moreover, the Q factor can be tuned from 610 to 1500 at each of the above four frequencies with negligible variation of inductance.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0