{"title":"基于不精确全加法器的近似加法器设计","authors":"Wenqiang Yang, Lunyao Wang, Kailei Li","doi":"10.1109/asid52932.2021.9651713","DOIUrl":null,"url":null,"abstract":"Approximate computing is a design way that sacrifices certain accuracy in exchange for circuit performance. The purpose is to reduce the circuit area, delay and power dissipation. In this paper, an approximate adder design method for Ripple Carry Adder (RCA) is proposed. The method mainly consists of three parts: (1) Building a library of inexact full adders with the parameters of error characteristic and area. (2) Using genetic algorithm to choose different approximate full adders for multi-bits RCAs under error distance constraints. (3) Error distance calculation by disjoint sharp product operation with logic cover. Compared with accurate RCA, the circuit area optimization of multi-bits approximate adder proposed in this paper can reach 36.21% when the mean error distance and normalized error distance are less than 1%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An Approximate Adder Design Based on Inexact Full Adders\",\"authors\":\"Wenqiang Yang, Lunyao Wang, Kailei Li\",\"doi\":\"10.1109/asid52932.2021.9651713\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Approximate computing is a design way that sacrifices certain accuracy in exchange for circuit performance. The purpose is to reduce the circuit area, delay and power dissipation. In this paper, an approximate adder design method for Ripple Carry Adder (RCA) is proposed. The method mainly consists of three parts: (1) Building a library of inexact full adders with the parameters of error characteristic and area. (2) Using genetic algorithm to choose different approximate full adders for multi-bits RCAs under error distance constraints. (3) Error distance calculation by disjoint sharp product operation with logic cover. Compared with accurate RCA, the circuit area optimization of multi-bits approximate adder proposed in this paper can reach 36.21% when the mean error distance and normalized error distance are less than 1%.\",\"PeriodicalId\":150884,\"journal\":{\"name\":\"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/asid52932.2021.9651713\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asid52932.2021.9651713","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Approximate Adder Design Based on Inexact Full Adders
Approximate computing is a design way that sacrifices certain accuracy in exchange for circuit performance. The purpose is to reduce the circuit area, delay and power dissipation. In this paper, an approximate adder design method for Ripple Carry Adder (RCA) is proposed. The method mainly consists of three parts: (1) Building a library of inexact full adders with the parameters of error characteristic and area. (2) Using genetic algorithm to choose different approximate full adders for multi-bits RCAs under error distance constraints. (3) Error distance calculation by disjoint sharp product operation with logic cover. Compared with accurate RCA, the circuit area optimization of multi-bits approximate adder proposed in this paper can reach 36.21% when the mean error distance and normalized error distance are less than 1%.