Design of A New Type of Regular Expression Matching Engine Based on FPGA

Abstract

In order to solve the problem that the computing power of processors in the post-Moore era cannot keep up with the speed of daily data generation, improve the ability of data retrieval and replacement, and ensure practicability, we learn from previous research and switch from traditional software to hardware to achieve regular matching. Based on the regular expression of the road characteristic, a regular matching hardware engine architecture is proposed and designed. Using RAM characteristics in this circuit, through different input configurations, there is no need to re-modify the circuit in the FPGA, so that it can achieve different pattern matching functions. It solves part of the generality problems caused by the diversity of modes, and satisfies common scenarios that require dynamic update of matching rules. And all matching processes are completed by only one basic core, saving a lot of logic resources. The processing speed is roughly 1 clock and 1 cycle to process 1 byte, which is close to the processing limit of digital circuits for single-byte data streams. Finally, the circuit is analyzed and compared with the circuit performance of typical research in the past, and the research work in the future is prospected.