Design of a column-parallel SAR/SS two-step hybrid ADC for sensor arrays

This paper presents a Successive Approximation Register/Single Slope (SAR/SS) two-step hybrid Analog-to-Digital Converter (ADC) circuit for sensor arrays. A 10-bit column-parallel SAR/SS ADC architecture with the area and speed performances compromise is proposed. A 6-bit SAR ADC performs the coarse quantization in the first step, and a SS ADC further performs the 4-bit fine quantization in the second step to complete the final data conversion. The ADC circuit is designed in TSMC 0.18 μm CMOS process with the 1.8 V power supply voltage. A sampling rate of 1 Msps is achieved at the clock frequency of 25 MHz, and the power consumption per channel is only 127.26 μW. The Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) of the ADC are -0.375 LSB/+0.375 LSB and - 0.375 LSB/+1.5 LSB, respectively. The Effective Number of Bits (ENOB) and Signal-to-Noise Ratio (SNR) are 9.44 bit and 60.49 dB, respectively. A Figure of Merit (FOM) of 183.22 fJ/conv is achieved.