一种基于FPGA的新型正则表达式匹配引擎设计

Nan Jiang, Ping Lin, Yulong He, Zhuozhi Tan, Jin Hu
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引用次数: 1

摘要

为了解决后摩尔时代处理器的计算能力跟不上日常数据生成速度的问题,提高数据检索和替换的能力,保证实用性,我们借鉴前人的研究,从传统的软件切换到硬件,实现规律匹配。基于道路特征的正则表达式,提出并设计了一种规则匹配的硬件引擎架构。在该电路中利用RAM的特性,通过不同的输入配置,无需在FPGA中重新修改电路,从而可以实现不同的模式匹配功能。它解决了部分模式多样性带来的通用性问题,满足了需要动态更新匹配规则的常见场景。并且所有的匹配过程仅由一个基本核心完成,节省了大量的逻辑资源。处理速度大致为1个时钟和1个周期处理1个字节,接近数字电路对单字节数据流的处理极限。最后,对该电路进行了分析,并与以往研究的典型电路性能进行了比较,对今后的研究工作进行了展望。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of A New Type of Regular Expression Matching Engine Based on FPGA
In order to solve the problem that the computing power of processors in the post-Moore era cannot keep up with the speed of daily data generation, improve the ability of data retrieval and replacement, and ensure practicability, we learn from previous research and switch from traditional software to hardware to achieve regular matching. Based on the regular expression of the road characteristic, a regular matching hardware engine architecture is proposed and designed. Using RAM characteristics in this circuit, through different input configurations, there is no need to re-modify the circuit in the FPGA, so that it can achieve different pattern matching functions. It solves part of the generality problems caused by the diversity of modes, and satisfies common scenarios that require dynamic update of matching rules. And all matching processes are completed by only one basic core, saving a lot of logic resources. The processing speed is roughly 1 clock and 1 cycle to process 1 byte, which is close to the processing limit of digital circuits for single-byte data streams. Finally, the circuit is analyzed and compared with the circuit performance of typical research in the past, and the research work in the future is prospected.
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