2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)最新文献_第2页

Porting RT-Thread to AnnikaSoC 将rt线程移植到AnnikaSoC

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651703

Zhirui Li, Jian Li, Yunrui Zhang, Jianyang Zhou, Zichao Guo

引用次数: 2

A Polynomial Multiplication Accelerator for Homomorphic Encryption using DGT 基于DGT的同态加密多项式乘法加速器

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651679

Jigang Yang, Zhenmin Li, Jingwei Ren, Xiaolei Wang, Wei Ni, Gaoming Du

{"title":"A Polynomial Multiplication Accelerator for Homomorphic Encryption using DGT","authors":"Jigang Yang, Zhenmin Li, Jingwei Ren, Xiaolei Wang, Wei Ni, Gaoming Du","doi":"10.1109/asid52932.2021.9651679","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651679","url":null,"abstract":"In modern information society, data security has become more and more critical. Homomorphic encryption is one of the best choice to solve the security problem of user data on the server because of its unique characteristics of allowing operations in the ciphertext. A homomorphic encryption scheme based on R-LWE is a hotspot in research and application. Polynomial multiplication in ℤp[x]/(xn+1) has brought significant attention recently. The key to accelerating the FV homomorphic encryption scheme is to accelerate the polynomial multiplication [1]. Traditional accelerators use the NTT algorithm. However, the conventional NTT scheme will cause the expansion of the number of terms after the operation, requiring additional modular reduction calculations. This paper presents a hardware accelerator for polynomial multiplication based on Discrete Galois Transform. Compared with traditional NTT, DGT cuts the length of the polynomial by half [2]. At the same time, a negative loop convolution is added to avoid additional modular reduction calculations. We designs a DGT-based hardware accelerator for polynomial multiplication on the ring. At the same time, a particular improvement is made to the DGT algorithm to make it friendly to hardware design and save some cycles. Experimental results show that our accelerator via DGT can effectively improve the multiplication speed of polynomials.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130437178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An Encryption Traffic Classification Method Based on ResNeXt 基于ResNeXt的加密流分类方法

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651686

Li Yidan, Chen Yanli, Chen Runze, Yin Lan, Ruan Fangming

引用次数: 1

[ASID 2021 Front matter] [ASID 2021前端事项]

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651491

引用次数: 0

A Novel Active Inductor with High Q Factor and Inductance and Mutually Independent Tuning Characteristic 一种具有高Q因数、高电感和相互独立调谐特性的新型有源电感

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651673

Yan Liang, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yamei Xu, Ziteng Cai

{"title":"A Novel Active Inductor with High Q Factor and Inductance and Mutually Independent Tuning Characteristic","authors":"Yan Liang, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yamei Xu, Ziteng Cai","doi":"10.1109/asid52932.2021.9651673","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651673","url":null,"abstract":"In this paper, a novel Active Inductor (AI) with high quality factor Q, high inductance L and mutually independent tuning characteristic is presented. It is mainly composed of three circuit blocks, and each circuit block is configured with an external voltage tunable terminal respectively. The high Q factor is achieved through the multiple MOSTETs negative resistance generation network connected between the positive and negative transconductors. Meanwhile, the high inductance is realized by the MOSFET variable capacitance block and the negative transconductor of the gyrator-C network in parallel. Additionally, the mutually independent tuning of Q and L each other is accomplished by coordinately varying three external tunable terminal voltages in three circuit blocks. Based on TSMC 0.18μm CMOS process, the novel AI is verified by Advanced Design System (ADS). The results show that at 4.8GHz, the peak Q factor can reach high up to 4086.06, and the inductance is as high as 273.62nH; at 4.5GHz, 4.8GHz and 5.1GHz, the Q value can be tuned greatly from 341.90 to 433.80, from 800.11 to 4086.06 and from 210.23 to 305.71 respectively, whereas the variation of L value is only 0.59%, 0.66% and 0.73%; Furthermore, under 4GHz, 4.8GHz and 5.4GHz, the L value can be tuned noticeably from 220.95nH to 247.72nH, from 298.00nH to 344.90nH and from 418.88nH to 511.34nH respectively, while the variation of the Q value is only 0.54%, 0.65% and 0.83%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125747507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Survey on Privacy-preserving Schemes for Vehicular Ad Hoc Networks 车载Ad Hoc网络隐私保护方案研究

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651711

Jianyang Cui, Ying Cai, Shaocheng Yang, Yu Zhang

引用次数: 0

Delay Cells for the Time-to-Digital Converter Implemented in FPGA 时间-数字转换器延迟单元的FPGA实现

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651717

Ze-Xian Chen, Zhiquan Wang, Guo Peng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu

引用次数: 0

HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC) 以hls为中心的动态可重构椭圆曲线密码的DSE及优化

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651483

Arthur Silitonga, Yigit Kiyak, J. Becker

{"title":"HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)","authors":"Arthur Silitonga, Yigit Kiyak, J. Becker","doi":"10.1109/asid52932.2021.9651483","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651483","url":null,"abstract":"Asymmetric cryptography is frequently used for key exchanges and signatures in today's secure data transmissions, for instance, Elliptic Curve Cryptography (ECC). This paper describes our ECC-based cryptographic algorithms implementation on a low-end All Programmable System-on-Chip (APSoC) imposed upon its Dynamic Partial Reconfiguration (DPR) due to the target platform's limited resource. Our asymmetric cryptosystem is based on elliptic curves defined over prime fields and utilizes a dynamic change of multiple key lengths. High-Level Synthesis (HLS) is the basis of our Design Space Exploration (DSE) and hardware implementation. The design is adapted to be algorithmically robust against numerous existing types of attacks. Referring to various possible key lengths, the provided modes are 192, 256, 384, and 512 bits during the design time. An optimized result in design time shows an implementation of the key length of 512 bits is inapplicable due to FPGA resources' plethora in our targeted APSoC. An optimized design is implemented and compared to particularly related works. Indeed, DPR usage brings an advantage that resources can be reused for ECC with various key lengths, other implementable crypto algorithms, or non-crypto designs.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128556698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simulators for Deep Neural Network Accelerator Design and Analysis: A Brief Review 深度神经网络加速器模拟器设计与分析综述

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651675

Mijing Sun, Li Xu, Zhenmin Li, Wei Ni, Gaoming Du, Xiaolei Wang, Yong-Sheng Yin

引用次数: 0

A Simple DDoS Defense Method Based SDN 一种基于SDN的简单DDoS防御方法

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI: 10.1109/asid52932.2021.9651724

Chen Runze, Ruan Fangming, Li Yidan, Yin Lan, Chen Yanli

引用次数: 3