Delay Cells for the Time-to-Digital Converter Implemented in FPGA

In this paper, an FPGA chip of Cyclone II is employed to investigate the delay characteristics of two TDC delay chains. In this study, the delay elements implemented by the L cell with different input channels were investigated by timing analysis in Chip Planner and by gate level simulation by ModelSim. According to our results, the time resolution of a single delay path can be 580 ps for LUTs configured with the D channel input. For the delay chain with two paths, the time resolution was about 490 ps with a combination of C- and D-channel assignments. It’s promising to further refine the time resolution of a TDC even in a Cyclone II chip.