Delay Cells for the Time-to-Digital Converter Implemented in FPGA

Ze-Xian Chen, Zhiquan Wang, Guo Peng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu
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Abstract

In this paper, an FPGA chip of Cyclone II is employed to investigate the delay characteristics of two TDC delay chains. In this study, the delay elements implemented by the L cell with different input channels were investigated by timing analysis in Chip Planner and by gate level simulation by ModelSim. According to our results, the time resolution of a single delay path can be 580 ps for LUTs configured with the D channel input. For the delay chain with two paths, the time resolution was about 490 ps with a combination of C- and D-channel assignments. It’s promising to further refine the time resolution of a TDC even in a Cyclone II chip.
时间-数字转换器延迟单元的FPGA实现
本文采用Cyclone II FPGA芯片对两种TDC延迟链的延迟特性进行了研究。在本研究中,通过Chip Planner中的时序分析和ModelSim的门级仿真,研究了L cell在不同输入通道下实现的延迟元件。根据我们的结果,对于配置了D通道输入的lut,单个延迟路径的时间分辨率可以达到580 ps。对于具有两条路径的延迟链,结合C通道和d通道分配,时间分辨率约为490 ps。即使在Cyclone II芯片中,也有望进一步改进TDC的时间分辨率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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