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1995 IEEE International SOI Conference Proceedings最新文献

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Results on noise examination of fully-depleted accumulation mode SOI pMOSFETs 全耗尽积累型SOI pmosfet的噪声检测结果
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526448
N. Lukvanchikova, M. Petrichuk, M. Garbar, E. Simoen, C. Claeys
{"title":"Results on noise examination of fully-depleted accumulation mode SOI pMOSFETs","authors":"N. Lukvanchikova, M. Petrichuk, M. Garbar, E. Simoen, C. Claeys","doi":"10.1109/SOI.1995.526448","DOIUrl":"https://doi.org/10.1109/SOI.1995.526448","url":null,"abstract":"Noise spectroscopy of levels is known to be a high-sensitive method for detection of defects, determination of their parameters and elucidation of their nature. This method is based on the analysis of generation-recombination noise that accompanies the processes of charge carrier capture and release on different centers in a semiconductor material or device. The purpose of this paper is to demonstrate the efficiency of the application of low-frequency noise methods for characterization of thin film fully-depleted accumulation mode SOI pMOSFETs.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128081048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Smart-power solenoid driver for 300/spl deg/C operation 智能电源电磁驱动器300/spl度/C操作
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526495
W. Maszara, D. Boyko, A. Caviglia, G. Goetz, J. B. Mckitterick, J. O'connor
{"title":"Smart-power solenoid driver for 300/spl deg/C operation","authors":"W. Maszara, D. Boyko, A. Caviglia, G. Goetz, J. B. Mckitterick, J. O'connor","doi":"10.1109/SOI.1995.526495","DOIUrl":"https://doi.org/10.1109/SOI.1995.526495","url":null,"abstract":"A 28 volt solenoid driver has been realized in partially-depleted SOI CMOS technology. The design features an n-channel high voltage MOSFET with an extended drain and a polysilicon field plate, and an on-board flyback diode, each capable of sinking 0.5 A of current and dissipating about 1 W of DC power. Pulse-width modulation (PWM) control maintains low dynamic power dissipation in the drive FET, while the externally selectable \"pull-in and hold\" function, which reduces the maximum operating current, helps to minimize the overall chip power. Saturation detection, current sense, and overcurrent fault outputs are provided to assist the system designer. The device was fabricated on SIMOX wafers with 340 nm of Si film using our 1.25 /spl mu/m CMOS SOI process with single level Ti/W interconnects and CoSi/sub 2/ contacts. Our Ti/W metallization, capped with Si/sub 3/N/sub 4/ for corrosion protection, has been evaluated to have a lifetime of /spl sim/16.7 years for 300/spl deg/C operation at 10/sup 6/ A/cm/sup 2/ (a 10% resistance increase was the definition of failure). The output power transistor has been formed with our standard CMOS process. Its gate dimensions were L=2 /spl mu/m and W=48,000 /spl mu/m, with a drain extension of 2.8 /spl mu/m.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129227293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Semi-insulating silicon for microwave integrated circuits 微波集成电路用半绝缘硅
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526476
S. Campbell
{"title":"Semi-insulating silicon for microwave integrated circuits","authors":"S. Campbell","doi":"10.1109/SOI.1995.526476","DOIUrl":"https://doi.org/10.1109/SOI.1995.526476","url":null,"abstract":"In silicon many of the transition metals have states near the center of the gap and so can be used to form semi-insulating wafers. In this paper calculated and measured resistivities of silicon as a function of substrate doping for gold doped n-type and silver doped p-type silicon are presented. Arrhenius plots of the effective diffusion coefficient of gold in Si/sub 3/N/sub 4/ diffusion barriers are also measured. A structure for forming semi-insulating silicon with an upper conductive layer using a wafer bonding technique is developed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123055373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Integrity of gate oxide on TFSOI materials TFSOI材料栅极氧化物的完整性
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526441
S.O. Hong, T. Wetteroth, H. Shin, S. Wilson, W.M. Huang, J. Foerstner, M. Racanelli, H. Shin, B. Hwang, D. Schroder
{"title":"Integrity of gate oxide on TFSOI materials","authors":"S.O. Hong, T. Wetteroth, H. Shin, S. Wilson, W.M. Huang, J. Foerstner, M. Racanelli, H. Shin, B. Hwang, D. Schroder","doi":"10.1109/SOI.1995.526441","DOIUrl":"https://doi.org/10.1109/SOI.1995.526441","url":null,"abstract":"The quality of gate oxides on Thin-Film-Silicon-On-Insulator (TFSOI) substrates is essential for the development of TFSOI technologies. Compared with the extensive work on device characterization and circuit performance, however, data in this area are still limited. This paper presents a gate oxide integrity (GOI) study on both SIMOX (Separation-by-IMplantation-of-OXygen) and BESOI (Bonded-Etched-back-SOI) substrates. The effect of wafer polishing to reduce the initial surface micro-roughness is also discussed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of silicon device processes aimed for silicon-on-diamond material 针对金刚石上硅材料的硅器件工艺评价
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526482
A. Soderbarg, B. Edholm, S. Bengtsson
{"title":"Evaluation of silicon device processes aimed for silicon-on-diamond material","authors":"A. Soderbarg, B. Edholm, S. Bengtsson","doi":"10.1109/SOI.1995.526482","DOIUrl":"https://doi.org/10.1109/SOI.1995.526482","url":null,"abstract":"Silicon-on-Diamond (SOD) is a candidate for the next generation of SOI materials, especially for applications requiring high heat spreading capability. Undoped diamond is a highly electrically insulating material at temperatures below 600 K. Resistivities above 10/sup 13/ /spl Omega/cm (at 10 V) and breakdown fields above 10/sup 7/ V/cm have been reported. Diamond conducts heat about 10 times better than silicon and more than 1000 times better than silicon dioxide. In this paper, necessary process modifications for successful manufacturing of devices on SOD-materials are discussed and evaluated.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122625430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits 先进的0.5 /spl μ m CMOS/SOI技术，适用于实用的超高速和低功耗电路
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526453
T. Ipposhi, T. Iwamatsu, Y. Yamaguchi, K. Ueda, H. Morinaka, K. Mashiko, Y. Inoue, T. Hirao
{"title":"An advanced 0.5 /spl mu/m CMOS/SOI technology for practical ultrahigh-speed and low-power circuits","authors":"T. Ipposhi, T. Iwamatsu, Y. Yamaguchi, K. Ueda, H. Morinaka, K. Mashiko, Y. Inoue, T. Hirao","doi":"10.1109/SOI.1995.526453","DOIUrl":"https://doi.org/10.1109/SOI.1995.526453","url":null,"abstract":"Thin-film SOI MOSFETs offer high-speed and low-power characteristics due to reduced junction capacitance and reduced back-gate-bias effect. Therefore, thin SOI devices have been considered to be candidates for element transistor structures used in high-speed and low-power CMOS LSIs. In order to proceed to the stage of commercial application, it is necessary to demonstrate the effectiveness of SOI devices in various kinds of practical circuits. In this paper, we report an advanced 0.5 /spl mu/m CMOS/SOI technology and demonstrate ultrahigh-speed and low-power operation in two kinds of typical circuits: frequency divider and adder.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127182185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of implant dose on formation of buried-oxide Si islands in low-dose SIMOX 植入剂量对低剂量SIMOX中埋藏氧化物硅岛形成的影响
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526489
S. Bagchi, J.D. Lee, S. Krause, P. Roitman
{"title":"Effect of implant dose on formation of buried-oxide Si islands in low-dose SIMOX","authors":"S. Bagchi, J.D. Lee, S. Krause, P. Roitman","doi":"10.1109/SOI.1995.526489","DOIUrl":"https://doi.org/10.1109/SOI.1995.526489","url":null,"abstract":"There are still important issues that remain on the microstructure of low-dose SIMOX that may affect its quality and performance as an SOI material. These issues include the presence of crystalline defects in the top Si layer and the presence of Si islands in the buried oxide (BOX) which can severely degrade dielectric properties. While the reasons for crystalline defect formation have been recently determined, the mechanism(s) of Si island formation in the BOX are still unclear. Such understanding could assist in improved processing for fabricating high quality BOX layers in low-dose SIMOX. In this paper we report on the effect of implant dose on the microstructural changes found during Si island formation.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Surface mobility of SOI MOSFET's in the high temperature range: modelling and experiment 高温范围内SOI MOSFET的表面迁移率:建模与实验
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526451
G. Reichert, T. Ouisse, J. Pelloie, S. Cristoloveanu
{"title":"Surface mobility of SOI MOSFET's in the high temperature range: modelling and experiment","authors":"G. Reichert, T. Ouisse, J. Pelloie, S. Cristoloveanu","doi":"10.1109/SOI.1995.526451","DOIUrl":"https://doi.org/10.1109/SOI.1995.526451","url":null,"abstract":"The temperature range of silicon components may be substantially extended by using SOI devices. In this paper, we propose a new physical definition of the usual parameters appearing in the empirical models used for expressing the surface mobility. We also present a thorough experimental study of the mobility in thin film SOI MOSFET's, in the temperature range 298-623K. All data agree with the theoretical model, which may thus be used for a physical interpretation of the results from room to high temperature.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125640398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Programming and erase with floating-body for high density low voltage flash EEPROM fabricated on SOI wafers 在SOI晶圆上制造高密度低压闪存EEPROM的浮体编程和擦除
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526494
M. Chi, A. Bergemont
{"title":"Programming and erase with floating-body for high density low voltage flash EEPROM fabricated on SOI wafers","authors":"M. Chi, A. Bergemont","doi":"10.1109/SOI.1995.526494","DOIUrl":"https://doi.org/10.1109/SOI.1995.526494","url":null,"abstract":"The new portable computing and telecommunications market requires high performance, low power, high density electrically reprogrammable non-volatile memories. Memories integrated with information handling circuits on SOI wafers can offer significant advantages for high speed computation, better isolation, lower leakage, better noise immunity, and excellent CMOS latch-up margin. A NOR Virtual Ground (NVG) flash memory cell fabricated on an SOI wafer is considered. The fabrication process for NVG on SOI can be unchanged if the silicon thickness of the SOI wafer is properly chosen and doped, such that the N+ bit-line (Source/Drain) touches the oxide layer. One important feature of cells on SOI is that it is difficult to ground the p-body of cell and it will be left floating during all memory operations. Therefore, it is important to study the effect of the floating body on channel-hot-electron (CHE) programming and Fowler-Nordheim (F-N) channel erase used in NVG flash memory.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130590303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure 采用侧触点结构实现高介电常数栅极绝缘体的超薄SOI MOSFET的最小寄生电阻
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526479
H. Shimada, T. Ohmi
{"title":"Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure","authors":"H. Shimada, T. Ohmi","doi":"10.1109/SOI.1995.526479","DOIUrl":"https://doi.org/10.1109/SOI.1995.526479","url":null,"abstract":"Since the interconnect capacitance almost maintains the same level even with shrinking device dimension, high current drive of a transistor is required for ultra-high speed operation. Although the ultra-thin SOI MOSFET is a promising candidate for ultra-small devices, its enormous parasitic resistance is a significant problem. The reduction of the parasitic resistance is a key issue in achieving high-performance ultra-thin SOI devices. In this study, a lateral contact structure, unique to SOI devices, with ultra-low contact resistance, is proposed for realizing ultimate low parasitic resistance.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114409416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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