1995 IEEE International SOI Conference Proceedings最新文献_第4页

Single crystalline silicon thin film transistors fabricated on Corning 7059 在康宁7059上制造的单晶硅薄膜晶体管

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526514

F. Plais, O. Huet, P. Legagneux, D. Pribat, A. Auberton-Herve, T. Barge

{"title":"Single crystalline silicon thin film transistors fabricated on Corning 7059","authors":"F. Plais, O. Huet, P. Legagneux, D. Pribat, A. Auberton-Herve, T. Barge","doi":"10.1109/SOI.1995.526514","DOIUrl":"https://doi.org/10.1109/SOI.1995.526514","url":null,"abstract":"Direct-view active matrix liquid crystal displays (AMLCDs) are now fabricated in very large volumes using amorphous silicon (a-Si:H) technology. For this purpose, high temperature polysilicon technology is currently used in Japan, with the active matrix fabricated on a quartz substrate. However, quartz substrates of display quality are rather expensive and low temperature polysilicon technology on glass substrates using laser annealing has been introduced as one possible alternative. Recently the transfer of single-crystalline Si layers on glass has been reported. In this case, circuits are fabricated on SOI substrates obtained by a zone melting recrystallisation process and transfered on the glass after completion of almost all the processing steps. This technique is of interest, as high temperature processing steps and fine design rules can be utilized. The main drawback of the technique is that the transfer operation is the final step. We propose an alternative and new technique based on the transfer before processing of a single crystalline Si layer on glass. Processing is subsequently performed at low temperature, using technological steps developed for the fabrication of low temperature polysilicon devices. A SIMOX substrate is thermally oxydized and then bonded at 450/spl deg/C to the glass substrate (Corning 7059 or 1737). The silicon substrate and the thin buried oxide are then removed by a combination of mechanical and chemical etching.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

SOI CMOS front-end technology: options and tradeoffs SOI CMOS前端技术:选择和权衡

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526431

D. Antoniadis

{"title":"SOI CMOS front-end technology: options and tradeoffs","authors":"D. Antoniadis","doi":"10.1109/SOI.1995.526431","DOIUrl":"https://doi.org/10.1109/SOI.1995.526431","url":null,"abstract":"There is general agreement that SOI CMOS has the potential of becoming a mainstream technology for future high performance and low-power logic applications. For this to be fulfilled, SOI CMOS technology should be able to support the design and manufacturing of complex future microprocessors. Then, from the design standpoint, SOI CMOS should be nearly identical to bulk CMOS, so that design tools, methodologies, and functional blocks can all be transferred with minimal perturbation. From the manufacturing standpoint, SOI CMOS should produce acceptable yields in circuits with 10 to 100 M transistors which will require process robustness latitude, scalability, and cost equivalent to or better than bulk. From the circuit design standpoint it is generally acknowledged that fully-depleted (FD) MOSFET's will provide the easier transfer path, because of their lack of significant floating-body (FB) effects under normal operation. However, scaled FD-MOSFET's require very thin SOI films which pose several technological challenges. On the other hand, partially-depleted (PD) MOSFET's are easier to make; indeed, their front-end technology can be imported from bulk with minimal perturbation. However, they display prominent FB effects which can pose problems in circuit design. The choice between the FD versus PD option is then recognized as the main SOI front-end technology tradeoff.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114648852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFETs PD/SOI mosfet中动态浮体充电诱导的低压瞬态双极效应

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526434

M. Pelella, J. Fossum, Dongwoo Suh, S. Krishnan, K. Jenkins

引用次数: 37

"Smart cut": a promising new SOI material technology “智能切割”:一种有前途的新型SOI材料技术

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526518

M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. Auberton-Herve, J. Lamure, T. Barge, F. Metral, S. Trucchi

引用次数: 57

The role of hydrogen in silicon wafer bonding: an infrared study 氢在硅晶圆键合中的作用:红外研究

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526513

M. Weldon, Y. Chabal, S. Christman, J. Bourcereau, C. A. Goodwin, C. Hsieh, S. Nakahara, R. Shanaman, W. G. Easter, L. Feldman

{"title":"The role of hydrogen in silicon wafer bonding: an infrared study","authors":"M. Weldon, Y. Chabal, S. Christman, J. Bourcereau, C. A. Goodwin, C. Hsieh, S. Nakahara, R. Shanaman, W. G. Easter, L. Feldman","doi":"10.1109/SOI.1995.526513","DOIUrl":"https://doi.org/10.1109/SOI.1995.526513","url":null,"abstract":"In this work, we utilize infrared absorption spectroscopy (IRAS) to probe the chemical purity of both wafer surfaces immediately prior to bonding and the wafer interface right after joining. The IRAS technique can give partial chemical information, particularly for hydrogen and can also indicate the nature of the interactions (van der Waals, H-bonding, chemical bonds). Experimentally, we probe the surfaces of Si wafers in two ways: either with multiple internal reflections (MIR) using the wafer itself to trap the IR radiation, or with MIR using a germanium plate to trap the IR radiation. The first approach is a convenient way to probe all vibrations above 1500 cm/sup -1/. The second is a sensitive way to access lower frequency vibrations (>700 cm/sup -1/), but is insensitive to the components parallel to the interface. To probe the interface of joined wafers, we use the technique of multiple internal transmission (MIT), using the joined Si wafers themselves to trap the IR radiation. This configuration is again limited to frequencies above 1500 cm/sup -1/, but its sensitivity to vibrations perpendicular to the interface is 20 times that of MIR.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125901934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optical characterization of silicon-on-insulator 绝缘体上硅的光学特性

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526483

G.G. Li, A. R. Forouhi, A. Auberton-Herve, A. Wittkower

引用次数: 2

Improvement of buried oxide quality in low-dose SIMOX wafers by high-temperature oxidation 高温氧化法改善低剂量SIMOX硅片埋地氧化物质量

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526507

K. Kawamura, T. Nakajima, I. Hamaguchi, T. Yano, Y. Nagatake, M. Tachimori

引用次数: 5

On-chip decoupling capacitor design to reduce switching-noise-induced instability in CMOS/SOI VLSI 片上去耦电容设计降低CMOS/SOI VLSI中开关噪声引起的不稳定性

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526480

L. K. Wang, Howard H. Chen

引用次数: 5

Avalanche hole injection into SIMOX oxide 雪崩孔注入SIMOX氧化物

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526490

R. J. Lambert, T. Bhar, H. Hughes, L. Allen

引用次数: 0

SOI DRAM: its features and possibility SOI DRAM的特点和可能性

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526491

Y. Yamaguchi, Y. Inoue

引用次数: 5