1995 IEEE International SOI Conference Proceedings最新文献_第3页

Analyses on the interface trap density and doping density of grounded-body SOI (GBSOI) nMOSFET 接地体SOI (GBSOI) nMOSFET的界面阱密度和掺杂密度分析

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526471

Jong-Son Lyu, W. Kang, H. J. Yoo

引用次数: 1

Impact of self-heating effects on the design of SOI devices versus temperature 自热效应对SOI器件设计的温度影响

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526487

J. Jomaah, G. Ghibaudo, F. Balestra, J. Pelloie

引用次数: 14

Transient behaviors in partially depleted thin film SOI devices 部分耗尽薄膜SOI器件的瞬态行为

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526432

H. Shin, I. Lim, M. Racanelli, W.M. Huang, J. Foerstner, B. Hwang, J. Whitfield, H. Shin, T. Wetteroth, S. Hong, S. Wilson, S. Cheng

引用次数: 2

Ultra thin SOI material by implantation of nitrogen and diffusion of oxygen to form a buried layer of silicon oxy-nitride 超薄SOI材料通过氮的注入和氧的扩散形成氮氧硅埋层

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526511

N. Meyyappan, T. Nakato, H. Takeuchi

引用次数: 1

Intrinsic low-field conduction in SIMOX buried oxides SIMOX埋地氧化物的本征低场传导

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526504

J. Yap, J. E. Chung

{"title":"Intrinsic low-field conduction in SIMOX buried oxides","authors":"J. Yap, J. E. Chung","doi":"10.1109/SOI.1995.526504","DOIUrl":"https://doi.org/10.1109/SOI.1995.526504","url":null,"abstract":"SOI technology is a prime candidate for replacing bulk Si in low-power VLSI CMOS applications. One of the most advanced SOI technologies is SIMOX. One potential problem with SIMOX SOI substrates is the intrinsic low-field conduction through the buried oxide (BOX), which is to be distinguished from defect-related \"piping\" current. Intrinsic low-level current, summed up over a very large chip area, could add up to a significant leakage component. In addition, low-level leakage poses a long-term reliability problem due to the potential for BOX charge trapping. Thus, a fundamental understanding of this low-field conduction is necessary in order to provide insight about the physical properties of the SIMOX BOX responsible for this current. In this paper, we present one of the first comprehensive studies of the electric-field, temperature, and time dependence of intrinsic low-level SIMOX BOX conduction characteristics for both single and multiple implant substrates. Based on the observed power-law time dependence, we believe that the low-level conduction is due to electron detrapping from pre-existing traps. The effect of Fowler-Nordheim (F-N) stress on low-field leakage is also examined. It was found that high-field stress can fill traps within the BOX which can then easily detrap at room temperature.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123825271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of SIMOX buried oxide leakage by direct measurements SIMOX埋地氧化物泄漏的直接测量分析

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526466

M. Anc, W. Krull

引用次数: 0

Step drift doping profile for high voltage DI lateral power devices 高压直喷侧功率器件的阶跃漂移掺杂剖面

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526499

R. Sunkavalli, A. Tamba, B. J. Baliga

{"title":"Step drift doping profile for high voltage DI lateral power devices","authors":"R. Sunkavalli, A. Tamba, B. J. Baliga","doi":"10.1109/SOI.1995.526499","DOIUrl":"https://doi.org/10.1109/SOI.1995.526499","url":null,"abstract":"The cell pitch of high voltage lateral power devices determines many important device performance specifications such as the area of the chip, on-state voltage drop and the maximum controllable current. Since the cell pitch of lateral power devices is determined by the long drift region lengths required to support high voltages in accordance with the RESURF principle, it is desirable to have a uniform lateral electric field distribution in the drift region to minimize the drift region length for a device with a given breakdown voltage. It is generally assumed that the breakdown voltage of DI RESURF devices scales up linearly with increasing drift region length till a limit associated with vertical breakdown is reached. However, 2D numerical simulations of the breakdown of DI PIN diodes indicate non-ideal electric field distribution in the drift region. Two techniques have been studied for achieving a more uniform electric field distribution in the drift region for DI lateral power devices. One technique involves the use of a SIPOS field plate over the drift region to spread the electric field uniformly. The other technique involves tailoring the drift region doping profile, so that the drift region charge increases linearly from the anode end to the cathode end.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132504688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Novel mesa isolation using CMP for planarization of 0.35/0.25 um SOI 利用CMP分离0.35/0.25 μ m SOI平面的新型台面

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526485

K. Joyner, I. Ali, R. Rajgopal, T. Houston

引用次数: 1

Implantation-induced-defect generation during device fabrication on a SIMOX substrate SIMOX基板上器件制造过程中植入诱导缺陷的产生

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526508

Hyoungsub Kim, Jeong-Seok Kim, D. Choi, Gon-sub Lee, Do-Hyung Kim, Kyupil Lee, Kinam Kim, Jong-Woo Park

引用次数: 0

Quantum-wire effects in thin and narrow SOI MOSFETs 细窄SOI mosfet中的量子线效应

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526463

X. Baie, J. Colinge, V. Bayot, E. Grivei

引用次数: 28