片上去耦电容设计降低CMOS/SOI VLSI中开关噪声引起的不稳定性

L. K. Wang, Howard H. Chen
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引用次数: 5

摘要

CMOS/SOI电路封装的电源噪声会导致性能下降、可靠性降低,甚至由于器件锁存问题而导致电路功能丧失。通过在电路附近适当地添加片上去耦电容,可以有效地缓解开关噪声问题,提高CMOS/SOI电路的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On-chip decoupling capacitor design to reduce switching-noise-induced instability in CMOS/SOI VLSI
The supply noise from the packaging of CMOS/SOI circuits can cause performance degradation, reliability reduction and even loss of circuit functionality due to the device latch-up problem. By properly adding on-chip decoupling capacitors in the proximity of the circuitry, we can effectively alleviate the switching noise problem and improve the performance of CMOS/SOI circuits.
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