2015 European Conference on Circuit Theory and Design (ECCTD)最新文献_第3页

Power-efficient estimation of silicon neuron firing rates with floating-gate transistors 用浮栅晶体管估算硅神经元放电速率的功率效率

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300005

Stephen Nease, E. Chicca

引用次数: 2

A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop 数字辅助的20MHz-600MHz 16相DLL，增强了动态增益控制回路

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300073

Arash Hejazi, S. Kazeminia, Roozbeh Abdollahi

{"title":"A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop","authors":"Arash Hejazi, S. Kazeminia, Roozbeh Abdollahi","doi":"10.1109/ECCTD.2015.7300073","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300073","url":null,"abstract":"In the proposed low-jitter delay locked loop (DLL), the analog charge pump (CP) is replaced by combination of binary accumulator (ACC) and digital-to-analog converter (DAC) to solve the problem of achieving small loop gains and mirroring small currents. Also, the problem of leakage currents during the lock state is removed when DAC provides a fixed analog voltage based on the ACC's output digital code. A simple lock detector is utilized to deactivate ACC and to generate a fixed control voltage for delay elements when the loop locks. Another loop is also applied to dynamically control loop-gain and lock time. Loop-Gain decreases (increases) when DLL moves toward (away from) the lock condition to not only guarantee the loop stability but, provide a fast lock time. Smaller jitter is expected on the generated phases comparing to the analog CPs. Here, a fixed control voltage is provided by DAC and the leakage currents cannot affect the control voltage. RMS jitter of less than 33.5ps and 1.6ps are achieved at 20MHz and 625MHz operating frequencies, respectively. Lock time is reduced from 38μs to 2μs at 20MHz and also from 900ns to 45ns at 600MHz where loop-gain is multiplied by 16, 8 and 4 for out of lock region. Total power consumption is 7.85mW at 1.8V supply voltage in a 0.18μm CMOS process.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115787312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A path towards average-case silicon via asynchronous resilient bundled-data design

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300102

P. Beerel, Ney Laert Vilar Calazans

{"title":"A path towards average-case silicon via asynchronous resilient bundled-data design","authors":"P. Beerel, Ney Laert Vilar Calazans","doi":"10.1109/ECCTD.2015.7300102","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300102","url":null,"abstract":"The periodic nature of the global clock in traditional synchronous designs forces circuits to be margined for the worst possible case of process, voltage, temperature, and data conditions. This constrains the silicon to operate at worst-case frequencies and at conservative supply voltages. Resilient architectures promise to remove these margins, by detecting and correcting timing errors when they occur, thereby creating the potential to achieve real average-case operation. However, synchronous resilient schemes previously proposed can suffer from multiple issues, including being susceptible to metastability and requiring often complex changes to the architecture to support replay-based recovery from timing errors. These problems respectively lead to circuit failures and/or incur high timing penalties when errors occur. This paper reviews a recently proposed asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. It also describes some open issues and new research opportunities this template presents, including automation problems to target average-case operation, specific circuit optimizations to minimize resiliency overhead, and the need for new test procedures to tune delay lines and screen out bad chips.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126671232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits 带附加结传感器的补偿电路，以提高CMOS集成电路的锁存抗扰度

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300129

H. Tsai, M. Ker

引用次数: 1

Power-efficient time-to-digital converter for all-digital frequency locked loops 功率高效的时间-数字转换器，用于全数字锁频环

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300008

Muhammad Touqir Pasha, N. Andersson, M. Vesterbacka

引用次数: 3

Complex behavior in memristor circuits based on static nonlinear two-ports and dynamic bipole 基于静态非线性双端口和动态双极的忆阻电路的复杂行为

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300050

Jacopo Secco, M. Biey, F. Corinto, A. Ascoli, R. Tetzlaff

引用次数: 4

Memristor state-space embedding 忆阻器状态空间嵌入

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300040

W. Dghais, L. N. Alves, J. Mendes, Jonathan Rodriguez, J. Pedro

引用次数: 2

Surfing front-end architectures for ultrasound imaging systems 超声成像系统的冲浪前端架构

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300006

P. Wang, T. Ytterdal, T. Halvorsrod

{"title":"Surfing front-end architectures for ultrasound imaging systems","authors":"P. Wang, T. Ytterdal, T. Halvorsrod","doi":"10.1109/ECCTD.2015.7300006","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300006","url":null,"abstract":"This paper proposes two surfing architectures of the front-end for cardiac ultrasound imaging systems by removing the high voltage (HV) transmitter/receiver (Tx/Rx) switch in traditional ultrasound imaging systems, and connecting the input and the local ground of the Rx to the output of the Tx directly. Both advantages and challenges are presented. During the emitting phase, the Rx is on reset mode and voltages at all internal nodes in the Rx will follow the transmitting pulse, and this phenomenon exhibits the Rx is in the surf as the transmitting pulse. By removing the Tx/Rx switch, the Rx can avoid saturating status during the pulse emitting phase in Tx, and can receive the reflected echo signals in an efficient way after the emitting phase. While the input of the Rx connecting to the PZT transducer directly without the Tx/Rx switch, the received echo signals will not be distorted by the Tx/Rx switch, and the switched-capacitor (SC) front-end of the Rx can be relaxed in the design. Currently the bulk CMOS technology may not support this architecture because of its intrinsic process limitation and relatively large parasitic capacitance of the PN junctions. SOI CMOS technology could be a feasible CMOS technology because its parasitic capacitance of the PN junction is much smaller and its process is different from the bulk CMOS technology. The simulation is based on an inverter-based SC amplifier in a high voltage 0.18 μm 50 V/1.8 V bulk CMOS technology, and a HV switch is based on a model which cannot be implemented in a bulk CMOS technology.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128420278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overview of hardware trojan detection and prevention methods 硬件木马检测和预防方法概述

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300077

Julien Francq, Florian Frick

引用次数: 3

Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems 集成压电- mems能量收集电源管理系统的高效CMOS整流器设计

2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300010

Martin Nielsen-Lönn, P. Harikumar, J. Wikner, A. Alvandpour

{"title":"Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems","authors":"Martin Nielsen-Lönn, P. Harikumar, J. Wikner, A. Alvandpour","doi":"10.1109/ECCTD.2015.7300010","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300010","url":null,"abstract":"MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134252562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4