Power-efficient time-to-digital converter for all-digital frequency locked loops

Abstract

An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops is presented. The selected architecture uses a Vernier delay line where the commonly used D flip-flops are replaced with a single enable transistor in the delay elements. This architecture allows for an area efficient and power efficient implementation. The dynamic range of the TDC is extended by using a 6-bit gray counter. A prototype chip has been implemented in a 65 nm CMOS process with an active core area of 75μm × 120μm. The time resolution is 5.7 ps with a power consumption of 1.85 mW measured at 50 MHz sampling frequency.