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Hardware property checker for run-time Hardware Trojan detection 用于运行时硬件木马检测的硬件属性检查器
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300085
X. Ngo, J. Danger, S. Guilley, Zakaria Najm, Olivier Emery
{"title":"Hardware property checker for run-time Hardware Trojan detection","authors":"X. Ngo, J. Danger, S. Guilley, Zakaria Najm, Olivier Emery","doi":"10.1109/ECCTD.2015.7300085","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300085","url":null,"abstract":"Nowadays, Hardware Trojans (HTs) become a real threat because of IC design and fabrication outsourcing trend. In the state of the art, many efforts were devoted to counter this threat, especially at netlist level. However, some clever HTs are actually a combination between a hardware and a software vulnerability, which, together, allow an exploitation. In this paper, we intend to detect such advanced HT, by resorting to a run-time detection. This method consists in identifying some high-level and critical behavioral invariants, and by checking them during the circuit operation. The assertion and Property Specification Language (PSL) is used to describe the properties to be checked. Then, a Hardware Property Checker (HPC) is created and integrated in the IC in order to verify these properties in runtime. We discuss how to define the critical properties for HPC. We also explain how this method is complementary with others, especially how the Hardware Checker can itself be protected against a tampering attempt. A case of study on LEON processor was performed to demonstrate the feasibility of this detection technique.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"61 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114003736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Clock phase imbalance and phase noise in RF N-path filters 射频n径滤波器中的时钟相位不平衡和相位噪声
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300062
Fahad Qazi, J. Dabrowski
{"title":"Clock phase imbalance and phase noise in RF N-path filters","authors":"Fahad Qazi, J. Dabrowski","doi":"10.1109/ECCTD.2015.7300062","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300062","url":null,"abstract":"The quality of RF N-path filtering is limited by the performance of the involved multiphase clock. The paper presents analysis of critical clock imperfections. The phase imbalance that gives rise to an extra image band located at second harmonic frequency is analyzed by a linear periodically varying (LPV) model of a 4-path filter where the respective rejection ratio is estimated and verified by simulation. We also analyze the clock phase noise and devise that the reciprocal mixing is not diminished by the attained blocker rejection, however, in this case one can benefit from band limitation by the output capacitance of the driving transconductance amplifier (LNTA). The analysis is supported by simulation results.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133453737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection 保护环布局对堆叠低压PMOS高压ESD防护的影响
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300108
S. Liao, Kai-Neng Tang, M. Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin
{"title":"Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection","authors":"S. Liao, Kai-Neng Tang, M. Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin","doi":"10.1109/ECCTD.2015.7300108","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300108","url":null,"abstract":"Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134574448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Thermal load analysis and real time hot spots recognition in TOKAMAK using cellular nonlinear networks 基于元胞非线性网络的托卡马克热负荷分析与实时热点识别
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300126
F. Battaglia, A. Buscarino, C. Corradino, L. Fortuna, M. Frasca, M. Apicella, G. Mazzitelli
{"title":"Thermal load analysis and real time hot spots recognition in TOKAMAK using cellular nonlinear networks","authors":"F. Battaglia, A. Buscarino, C. Corradino, L. Fortuna, M. Frasca, M. Apicella, G. Mazzitelli","doi":"10.1109/ECCTD.2015.7300126","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300126","url":null,"abstract":"A recent innovative technology in the field of plasma-wall interaction in nuclear fusion experiments is represented by the Liquid Lithium Limiter (LLL), a Limiter with a cooling system based on Liquid Lithium. Since its performance depends on the spatial temperature distribution, a thermal load analysis is important for long term developments. Furthermore, temperature is often not uniformly distributed leading to hot spots formation, that should be detected in real time to avoid any plasma disruptions. In this paper, an approach based on the definition of a suitable Cellular Nonlinear Network algorithm for the real-time image processing of thermal images taken during a plasma experiment is introduced. It allows both to map the LLL temperature and to detect hot spots over the limiter surface. Offline testing of the proposed procedure reveals the effectiveness of the approach paving the way to the modeling of the limiter surface temperature providing reliable information.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132007407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
New image denoising method using multiple-minimum cuts based on maximum-flow neural network 基于最大流量神经网络的多重最小分割图像去噪新方法
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300086
Masatoshi Sato, T. Otake, H. Aomori, Mamoru Tanaka
{"title":"New image denoising method using multiple-minimum cuts based on maximum-flow neural network","authors":"Masatoshi Sato, T. Otake, H. Aomori, Mamoru Tanaka","doi":"10.1109/ECCTD.2015.7300086","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300086","url":null,"abstract":"In recent years, graph-cuts has became increasingly useful methods for image processing problems such as the image denoising, the image segmentation, the stereo matching and so on. In graph-cuts, a given image is replaced by a grid graph with defined edge weights according to each problem, and the image is processed by using a minimum cut of the graph. Therefore, the most part of the graph-cuts algorithm is based on the typical minimum cut algorithm. However, graph-cuts still has two issues of processing time and accuracy of output images because of the conventional minimum cut algorithm. Moreover, the relation between the high-speed processing and the improvement of accuracy is basically a trade-off relation. In this research, we propose a new image denoising method using multiple-minimum cuts based on the maximum-flow neural network (MF-NN) which is our proposed minimum cut algorithm based on the nonlinear resistive circuit analysis. The MF-NN has two unique features not shared by the conventional minimum cut algorithm. One is that multiple-minimum cuts can be obtained simultaneously, and the other is to be suitable for hardware implementation. By using the MF-NN's features, the we find novel solutions for two issues of the conventional graph-cuts.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"48 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132913798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Voltage-mode all-pass filter passive scheme based on floating negative resistor and grounded capacitor 基于浮动负电阻和接地电容的电压型全通滤波器无源方案
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300056
N. Herencsar, J. Koton, K. Vrba, S. Minaei, I. C. Göknar
{"title":"Voltage-mode all-pass filter passive scheme based on floating negative resistor and grounded capacitor","authors":"N. Herencsar, J. Koton, K. Vrba, S. Minaei, I. C. Göknar","doi":"10.1109/ECCTD.2015.7300056","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300056","url":null,"abstract":"In this paper, a new RC circuit realization of voltage-mode (VM) first-order all-pass filter (APF) is presented. The proposed VM APF scheme is composed of a single grounded capacitor, three resistors with one being negative. The main advantage of the circuit is the common ground terminal between the input and the output. For proper functionality passive element matching is required and the negative resistance is implemented with Arbel-Goldminz operational transconductance amplifier. The theoretical results are verified with SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122786265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
About quantization of audio signals for wildlife intruder detection systems 野生动物入侵检测系统中音频信号的量化研究
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300036
L. Grama, C. Rusu
{"title":"About quantization of audio signals for wildlife intruder detection systems","authors":"L. Grama, C. Rusu","doi":"10.1109/ECCTD.2015.7300036","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300036","url":null,"abstract":"In this work we study the quantization of audio signals for a zero-crossing method recently used to detect intruders in wildlife areas. This method implements two descriptors: D (represents the number of samples between two real zeros) and S (represents the number of points of local minima/maxima between two consecutive real zeros). We show using experimental results that in the proposed audio based wildlife intruder detection framework, the number of D/S pairs are almost constant till the number of bits used for quantization is less than six.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"127 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120987670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
4 Sub-/near-threshold flip-flops with application to frequency dividers 应用于分频器的亚/近阈值触发器
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300058
A. Vatanjou, T. Ytterdal, S. Aunet
{"title":"4 Sub-/near-threshold flip-flops with application to frequency dividers","authors":"A. Vatanjou, T. Ytterdal, S. Aunet","doi":"10.1109/ECCTD.2015.7300058","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300058","url":null,"abstract":"Four different flip-flops dimensioned for subthreshold operation have been designed and implemented in layouts. The four full custom, race-free, D-flip-flops were implemented in a standard 65 nm CMOS process and verified by measurements, when used in 2 divide-by-3 circuits. The first frequency divider, using standard topologies, demonstrated functionality down to a supply voltage of 132 mV, while the second variant, based on a recently proposed “`slice-based'” approach, was functional for a supply voltage down to 137 mV. The frequency divider using traditional 4-transistor NAND and NOR topologies had lower energy per operation than the alternative 8-transistor NAND and NOR implementation. At 0.1 MHz, the figures were about 2.1 fJ and 3.5 fJ, respectively. For supply voltages from 0.2 to 1.2 V, a static flip-flop using 8-transistor NOR-gates plus one inverter had the lowest static power consumption among the 4 flip-flops.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123465726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of current mode front-end amplifiers with optimal timing performance for high-gain photodetectors 高增益光电探测器中具有最佳时序性能的电流型前端放大器设计
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300092
F. Ciciriello, F. Corsi, F. Licciulli, C. Marzocca, G. Matarrese
{"title":"Design of current mode front-end amplifiers with optimal timing performance for high-gain photodetectors","authors":"F. Ciciriello, F. Corsi, F. Licciulli, C. Marzocca, G. Matarrese","doi":"10.1109/ECCTD.2015.7300092","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300092","url":null,"abstract":"When a current-mode approach is exploited to readout high-gain photodetectors, preamplifiers with input resistance as low as possible and very large bandwidth are commonly used to optimize the time resolution of the detection system. In our study we show that, due to the effects of the parasitic inductance associated with the interconnection between the detector and the front-end electronics, extremely low input resistance and very large bandwidth are not optimal design choices, as commonly assumed. To support the study, we refer as an example to a detection system based on a Photo-Multiplier Tube read-out by a simple BJT common base current buffer and demonstrate by simulation the existence of values of input resistance and bandwidth which optimize the timing accuracy of the system.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122575139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Finding all DC solutions of nonlinear circuits using parallelogram LP test 用平行四边形LP测试求非线性电路的所有直流解
2015 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2015-10-19 DOI: 10.1109/ECCTD.2015.7300124
K. Yamamura, S. Ishiguro
{"title":"Finding all DC solutions of nonlinear circuits using parallelogram LP test","authors":"K. Yamamura, S. Ishiguro","doi":"10.1109/ECCTD.2015.7300124","DOIUrl":"https://doi.org/10.1109/ECCTD.2015.7300124","url":null,"abstract":"An efficient algorithm is proposed for finding all DC solutions of nonlinear circuits using linear programming. This algorithm is based on a simple test (termed the LP test) for nonexistence of a solution to a system of nonlinear equations in a given region. In the conventional LP test, a system of nonlinear equations is transformed into a linear programming problem by surrounding component nonlinear functions by rectangles. Then, the emptiness or nonemptiness of the feasible region is checked by the dual simplex method. In this paper, we propose a new LP test algorithm using both rectangles and parallelograms, and shows that the proposed algorithm is more efficient than the conventional algorithms using rectangles only or parallelograms only.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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