Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits

Abstract

A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup trigger current can be detected, and then the I/O or ESD-protection devices are used to generate the compensation current that decrease the perturbation to the internal circuits. The proposed design has been successfully verified in a 0.5-μm BCD process to improve latchup immunity.