A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop

In the proposed low-jitter delay locked loop (DLL), the analog charge pump (CP) is replaced by combination of binary accumulator (ACC) and digital-to-analog converter (DAC) to solve the problem of achieving small loop gains and mirroring small currents. Also, the problem of leakage currents during the lock state is removed when DAC provides a fixed analog voltage based on the ACC's output digital code. A simple lock detector is utilized to deactivate ACC and to generate a fixed control voltage for delay elements when the loop locks. Another loop is also applied to dynamically control loop-gain and lock time. Loop-Gain decreases (increases) when DLL moves toward (away from) the lock condition to not only guarantee the loop stability but, provide a fast lock time. Smaller jitter is expected on the generated phases comparing to the analog CPs. Here, a fixed control voltage is provided by DAC and the leakage currents cannot affect the control voltage. RMS jitter of less than 33.5ps and 1.6ps are achieved at 20MHz and 625MHz operating frequencies, respectively. Lock time is reduced from 38μs to 2μs at 20MHz and also from 900ns to 45ns at 600MHz where loop-gain is multiplied by 16, 8 and 4 for out of lock region. Total power consumption is 7.85mW at 1.8V supply voltage in a 0.18μm CMOS process.