1996 Proceedings 46th Electronic Components and Technology Conference最新文献_第9页

Thermal fatigue reliability enhancement of plastic ball grid array (PBGA) packages 提高塑料球栅阵列(PBGA)封装的热疲劳可靠性

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550889

A. R. Syed

引用次数: 55

Board and system level effects on plastic package thermal performance 板级和系统级对塑料封装热性能的影响

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550754

T. Zhou, M. Hundt

引用次数: 8

Low-stress leadframe design for plastic IC packages 塑料IC封装的低应力引线框架设计

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550500

N. Bhandarkar, L. Beng

引用次数: 0

Foil covered PACkage (FPAC): a new package concept 铝箔包装(FPAC):一种新的包装概念

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550896

Y. Hotta, H. Sigyo, S. Kondo, S. Oizumi

引用次数: 1

Compatibility of lead-free solders with lead containing surface finishes as a reliability issue in electronic assemblies 无铅焊料与含铅表面处理的兼容性是电子组件的可靠性问题

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550885

P. Vianco, J. Rejent, I. Artaki, U. Ray, D. Finley, A. Jackson

{"title":"Compatibility of lead-free solders with lead containing surface finishes as a reliability issue in electronic assemblies","authors":"P. Vianco, J. Rejent, I. Artaki, U. Ray, D. Finley, A. Jackson","doi":"10.1109/ECTC.1996.550885","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550885","url":null,"abstract":"Enhanced performance goals and environmental restrictions have heightened the consideration for use of alternative solders as replacements for the traditional tin-lead (Sn-Pb) eutectic and near-eutectic alloys. However, the implementation of non-Pb bearing surface finishes may lag behind solder alloy development. A study was performed which examined the effect(s) of Pb contamination on the performance of Sn-Ag-Bi and Sn-Ag-Cu-Sb lead-free solders by the controlled addition of 63Sn-37Pb solder at levels of 0.5-8.0 Wt.%. Thermal analysis and ring-in-plug shear strength studies were conducted on bulk solder properties. Circuit board prototype studies centered on the performance of 20I/O SOIC gull wing joints. Both alloys exhibited declines in their melting temperatures with greater Sn-Pb additions. The ringing-plug shear strength of the Sn-Ag-Cu-Sb solder increased slightly with Sn-Pb levels while the Sn-Ag-Bi alloy experienced a strength loss. The mechanical behavior of the SOIC Sn-Ag-Bi solder joints reproduced the strength drop to Sn-Pb contamination; however, the strength levels were insensitive to 10,106 thermal cycles. The Sn-Ag-Cu-Sb solder showed a slight decrease in the gull wing joint strengths that was sensitive to the Pb content of the surface finish.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121286026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

PWB solder wettability after simulated storage 模拟存储后的PWB焊料润湿性

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550883

C.L. Hernadez, F. Hosking

{"title":"PWB solder wettability after simulated storage","authors":"C.L. Hernadez, F. Hosking","doi":"10.1109/ECTC.1996.550883","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550883","url":null,"abstract":"A new solderability test method has been developed at Sandia National Laboratories that simulates the capillary flow physics of solders' on circuit board surfaces. The solderability test geometry was incorporated on a circuit board prototype that was developed for a National Center for Manufacturing Sciences (NCMS) program. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, NCMS, and several PWB fabricators (AT&T, IBM, Texas Instruments, United Technologies/Hamilton Standard and Hughes Aircraft) to advance PWB interconnect technology. The test was used to investigate the effects of environmental prestressing on the solderability of printed wiring board (PWB) copper finishes. Aging was performed in a controlled chamber representing a typical indoor industrial environment. Solderability testing on as-fabricated and exposed copper samples was performed with the Sn-Pb eutectic solder at four different reflow temperatures (215, 230, 245 and 260/spl deg/C). Rosin mildly activated (RMA), low solids (LS), and citric acid-based (CA) fluxes were included in the evaluation. Under baseline conditions, capillary flow was minimal at the lowest temperatures with all fluxes. Wetting increased with temperature at both baseline and prestressing conditions. Poor wetting, however, was observed at all temperatures with the LS flux. Capillary flow is effectively restored with the CA flux.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Gallium alloy interconnects for flip-chip assembly applications 用于倒装芯片组装应用的镓合金互连

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550881

D. Baldwin, R. Deshmukh, C. S. Hau

{"title":"Gallium alloy interconnects for flip-chip assembly applications","authors":"D. Baldwin, R. Deshmukh, C. S. Hau","doi":"10.1109/ECTC.1996.550881","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550881","url":null,"abstract":"For miniature interconnection applications, innovative material systems based on gallium alloys offer potentially attractive alternatives over commonly used bonding materials, such as solders and conductive adhesives, without the reliability and environmental drawbacks. Gallium alloys are mechanically alloyed mixtures of a liquid metal and metallic powders, formed at room temperature which cure to form solid intermetallic interconnects. Through the course of this work, gallium alloys have been investigated for flip-chip interconnect applications. Specifically, this paper presents the results of a preliminary feasibility study demonstrating the applicability of gallium alloys as flip-chip on laminate interconnect materials. The topics covered include the test vehicle assembly process, reliability screening results, preliminary failure mode analysis, and interconnect microstructure analysis. To demonstrate preliminary feasibility and application, gallium alloyed with copper and nickel was used as micro-miniature interconnects between bare silicon chips and printed circuit boards. This initial study shows feasibility of such interconnects and the reliability tests demonstrate sufficient cyclic fatigue reliability in the presence of underfill material. Moreover, through the course of this work a new micro-dispensing technology for gallium alloys was developed which leverages existing industry infrastructure. This initial study represents a significant advancement in microelectronic interconnect materials unveiling the potential for an innovative lead-free interconnect alternative.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Design and development of a high performance PBGA package for the UltraSPARC-I/sup TM/ processor UltraSPARC-I/sup TM/处理器的高性能PBGA封装设计与开发

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517464

John A. Abbott, G. Hamilton, N. Kalidas, M. Murtuza, C. Thornton, S. Thomas, Y. Umeda, D. Malladi, D. Towne, S. Chao

引用次数: 1

Reliability and characterization of MLC decoupling capacitors with C4 interconnections 具有C4互连的MLC去耦电容器的可靠性和特性

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517415

D. Scheider, D. Hopkins, P. Zucco, Edward Moszczynski, M. Griffin, M. Takács, J. Galvagni

{"title":"Reliability and characterization of MLC decoupling capacitors with C4 interconnections","authors":"D. Scheider, D. Hopkins, P. Zucco, Edward Moszczynski, M. Griffin, M. Takács, J. Galvagni","doi":"10.1109/ECTC.1996.517415","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517415","url":null,"abstract":"Multilayer ceramic (MLC) capacitors are composite structures made of alternating layers of ceramic (dielectric material) and metal (electrodes). The dielectric material is barium titanate-based ceramic and the electrodes are made of platinum. C4 (controlled collapse chip connections) technology is used to provide multiple attachment points to substrates. A high dielectric constant of barium titanate-based ceramic helps to achieve a large capacitance/size ratio. The capacitance ranges from 32 nF to 100 nF in body sizes up to 1.85/spl times/1.6/spl times/0.85 mm. In this paper, we cover design, reliability and electrical characterization of capacitors with C4 interconnections. Reliability stress tests performed during qualification were designed to cover a wide range of field applications and included stress tests such as liquid to liquid thermal shock, moisture resistance and thermal cycles per Mil.Std., high temperature bias, temperature humidity bias and tensile pull. A visual inspection of parts post stress and physical analysis of unstressed parts were also performed. The parameters monitored during stress testing were: capacitance, leakage current and plate resistance. The electrical characterization measurements included effects of frequency, temperature and voltage. Inductance measurements were included based on a self-resonance technique.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115596367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A new flip-chip technology for high-density packaging 用于高密度封装的新型倒装芯片技术

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550814

D.L. Smith, A.S. Alimonda

引用次数: 50