1996 Proceedings 46th Electronic Components and Technology Conference最新文献_第8页

Investigation of stress singularity fields and stress intensity factors for interfacial delamination (an application of thermosetting polyimide for a tapeless lead-on-chip (LOC) package) 界面分层的应力奇异场及应力强度因子研究(热固性聚酰亚胺在无胶带片上铅封装中的应用)

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517421

M. Amagai

{"title":"Investigation of stress singularity fields and stress intensity factors for interfacial delamination (an application of thermosetting polyimide for a tapeless lead-on-chip (LOC) package)","authors":"M. Amagai","doi":"10.1109/ECTC.1996.517421","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517421","url":null,"abstract":"The reliability of semiconductor devices and packages used in microelectronics is compromised by interfacial delamination and homogenous cracking that is initiated at the edge of the interface between dissimilar materials during processing and stress tests. These failures have certain characteristics in that they begin at the stress singularity point. The knowledge of interfacial fracture mechanics is very important to the design for reliability of these devices and packages. In this paper, a model of stress singularity is proposed and applications of the model for the characterization of interfaces are subsequently presented. Examples are integrated circuit (IC) device interfaces and plastic package interfaces. These interfaces were mainly characterized with the order of stress singularity. Furthermore, this study demonstrates applications of the stress intensity factors for the stress singularity fields. The stress intensity factors were obtained from a r-/spl theta/ coordinate system, the order of stress singularity, the Dunders' parameters, and the extrapolation as a function of distance. The relationship between the stress intensity factors and the interfacial fracture toughness strength as a function of mode mixity was also investigated for delamination at the edge of the interface. The proposed numerical scheme was verified by the experiments on the lead-on-chip (LOC) package delamination in a soldering process.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"46 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120904983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Thermal and viscoelastic characterization of transfer-molded epoxy encapsulant during simulated post-mold cure 模拟模后固化过程中转移模压环氧密封剂的热和粘弹性特性

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550809

S. Chew

引用次数: 8

Recipe synthesis for PECVD SiO/sub 2/ films using neural networks and genetic algorithms 基于神经网络和遗传算法的PECVD SiO/ sub2 /薄膜配方合成

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550508

Seung-Soo Han, G. May

{"title":"Recipe synthesis for PECVD SiO/sub 2/ films using neural networks and genetic algorithms","authors":"Seung-Soo Han, G. May","doi":"10.1109/ECTC.1996.550508","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550508","url":null,"abstract":"Silicon dioxide films deposited by plasma-enhanced chemical vapor deposition PECVD) are useful as interlayer dielectrics for metal-insulator structures such as multichip modules. Due to the complex nature of particle dynamics within a plasma, it is difficult to determine the exact nature of the relationship between PECVD process conditions and their effects on critical output parameters. In this study, neural network process models are used in conjunction with genetic algorithms to determine the necessary process recipes to achieve novel film qualities. To characterize the PECVD process, SiO/sub 2/ films deposited in a plasma-Therm 700 series PECVD system under varying conditions are analyzed using a central composite experimental design. Parameters varied include substrate temperature, pressure, RF power, silane flow and nitrous oxide flow. Data from this experiment is used to train back-propagation neural networks to model deposition rate, refractive index, permittivity, film stress, wet etch rate, uniformity, silanol concentration, and water concentration. A recipe synthesis procedure is then performed using genetic algorithms, Powell's algorithm, the simplex method, and hybrid combinations thereof to generate the necessary deposition conditions to obtain novel film qualities, including zero residual stress, 0% non-uniformity, 0% impurities, and low permittivity. Recipes predicted by these techniques are verified by experiment, and the performance of each synthesis method is compared.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132931296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

The packaging of large spot-size optoelectronic devices 大点尺寸光电器件的封装

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517453

J. Collins, I. Lealman, P.J. Fiddyment, A. Thurlow, C. Ford, D. Rogers, C.A. Jones

引用次数: 6

The evaluation of fast-flow, fast-cure underfills for flip chip on organic substrates 有机基板上倒装芯片的快流、快固化底填料的评价

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517441

K. Wun, G. Margaritis

引用次数: 25

Advanced molding technique for optical transceivers 先进的光收发器成型技术

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.550876

S. Robinson, F. Anigbo, G. Shevchuk

{"title":"Advanced molding technique for optical transceivers","authors":"S. Robinson, F. Anigbo, G. Shevchuk","doi":"10.1109/ECTC.1996.550876","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550876","url":null,"abstract":"With the growing use of fiber optics in Local Area Networks (LANs), efforts to cost reduce the optical components has intensified. In general, optoelectronic components for Fiber Distributed Data Interface (FDDI) and Fiber Channel LANs have been LED-based Optical Data Links (ODLs). Due to the bi-directional nature of most links, the trend has been towards the integration of simplex optical transmitters and receivers into Optical Transceivers. Further cost reductions through the use of automated assembly processes such as two step overmolding have also been reported recently. In this paper, we propose a molding technique designed to further cost reduce optoelectronic devices. The technique involves the use of a one-step overmolding process to encapsulate the electronics and injection molded connector receptacle. The injection molded receptacle is designed to provide support and alignment for the Optical Sub-Assemblies (OSAs) prior to overmolding. With the electronics on its substrate (Leadframe/HIC), the optics on the receptacle, and the link between the optics and the electronics complete (wirebonded), the substrate and the receptacle are overmolded in one step. This technique eliminates the need for the first mold process inherent in the two stage overmolding technique. The one step method also removes the need for precision mold features required for optical port alignment and subsequent final assembly (necessary in the two step method). This method, however, combines five active components into one integrated unit-requiring the use of \"Known Good Die\" to ensure a trouble free device.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134143206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A straddle mount connector system attach process 一种跨座式安装连接器系统附加过程

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517431

R. Schluter, K.J. Pearsall, R. W. Burns

引用次数: 0

Effects of mold compound properties on lead-on-chip (LOC) package reliability during IR reflow IR回流过程中模具复合性能对片上铅封装可靠性的影响

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517374

Ji-Chen Yang, L. Weng, Goh Jing Sua, Yew Chee Kiang

{"title":"Effects of mold compound properties on lead-on-chip (LOC) package reliability during IR reflow","authors":"Ji-Chen Yang, L. Weng, Goh Jing Sua, Yew Chee Kiang","doi":"10.1109/ECTC.1996.517374","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517374","url":null,"abstract":"This paper reports the investigation into Lead-On-Chip (LOG) package cracking resistance, the effects of mold compound properties, and the package cracking predication. The vehicle for such investigation was a DRAM LOC package and four mold compounds under two IR reflow processes (220/spl deg/C and 260/spl deg/C). As the reliability of the LOC package is strongly dependent on the mechanical properties of the mold compound, great efforts were put into its characterizations. The mold compound characterization was conducted using an Instron Universal Tester with a temperature chamber which regulated the testing temperature from -60 to 260/spl deg/C. These characterizations included temperature dependence, loading speed effects, moisture effects, creep behaviour, etc. The linear elastic fracture mechanics method was used to predict package cracking resistance. This included obtaining mold compound fracture toughness through 3-point bending test at the IR reflow temperatures, finite element analysis to obtain package stress intensity factors at these conditions, and correlate with the package reliability test results.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129403166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Development of molded fine-pitch ball grid array (FPBGA) using through-hole bonding process 采用通孔键合工艺的成型细间距球栅阵列(FPBGA)的研制

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517465

S. Matsuda, K. Kata, H. Nakajima, E. Hagimoto

引用次数: 1

Measurement and simulation of simultaneous switching noise in the multi-reference plane package 多参考平面封装中同步开关噪声的测量与仿真

1996 Proceedings 46th Electronic Components and Technology Conference Pub Date : 1996-05-28 DOI: 10.1109/ECTC.1996.517456

S. Rosser, M. K. Kerr, C. S. Chang, J. Fang, Zhaoqing Chen, Yuzhe Chen

引用次数: 13