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Electrical Performance of Electronic Packaging - 2004最新文献

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Modeling the impact of power/ground via arrays on power delivery 模拟电源/地通过阵列对电力输送的影响
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407562
J.R. Miller, I. Novak
{"title":"Modeling the impact of power/ground via arrays on power delivery","authors":"J.R. Miller, I. Novak","doi":"10.1109/EPEP.2004.1407562","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407562","url":null,"abstract":"The impact of via arrays on power and ground planes is examined in This work. Measurements of the plane impedance were made on a 8/spl times/8 via array as a function of via pair location. The results from full-wave field solution are compared to measurement data and excellent correlation is obtained. The results show that the impedance and effective inductance is a strong function of location within the array. The lowest impedance and inductance is measured on the array perimeter. A 4 X increase in the impedance and inductance occurs at the array center. By parameterizing the antipad diameter in simulation it is found that the impedance increases sharply when the antipads overlap.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116678950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Methodology for expedient computation of semiconductor substrate noise coupling 半导体衬底噪声耦合的便捷计算方法
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407608
G. Manetas, A. Cangellaris
{"title":"Methodology for expedient computation of semiconductor substrate noise coupling","authors":"G. Manetas, A. Cangellaris","doi":"10.1109/EPEP.2004.1407608","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407608","url":null,"abstract":"A fast semi-analytical modeling methodology is proposed, for expedient computation of semiconductor substrate coupling between substrate contacts. The expediency of the method stems from its ability to calculate analytically the transfer resistance between two contacts for the case of a layered substrate. These transfer resistances are then used for the computation of a conductance matrix representation of the coupling between the contacts. The validity and accuracy of the proposed model are investigated through a series of numerical studies involving semiconductor substrates of properties pertinent to state-of-the-art ICs.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134571267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Overview of some options to create low-Q controlled-ESR bypass capacitors 创建低q控制esr旁路电容器的一些选项概述
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407546
I. Novak, S. Pannala, J.R. Miller
{"title":"Overview of some options to create low-Q controlled-ESR bypass capacitors","authors":"I. Novak, S. Pannala, J.R. Miller","doi":"10.1109/EPEP.2004.1407546","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407546","url":null,"abstract":"Low-Q bypass capacitors with controlled ESR offer the advantage of creating resonance-free power distribution networks (PDN) with low sensitivity to component tolerances, and achieving a predictable impedance profile with the minimum number of components. Low Q bypass capacitors, termed bypass resistors, can be created either by reducing the inductance of the part, and/or by raising the equivalent series resistance (ESR). In multi-layer capacitors, ESR can be raised by using resistive plates, and/or resistive terminations, or by adding resistance externally with low inductance. Low-resistance capacitor plates can be patterned outside the high-frequency current loop. In thin-film capacitors, ESR can also be raised by reducing the thickness of capacitor plates.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132765871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A fast evaluation of power delivery system input impedance of printed circuit boards with decoupling capacitors 带去耦电容的印刷电路板供电系统输入阻抗的快速评估
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407560
Jin Zhao, O. Mandhana
{"title":"A fast evaluation of power delivery system input impedance of printed circuit boards with decoupling capacitors","authors":"Jin Zhao, O. Mandhana","doi":"10.1109/EPEP.2004.1407560","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407560","url":null,"abstract":"A fast power delivery system input impedance evaluation methodology for printed circuit board decoupling capacitor placement study is presented in This work. The methodology is based on electrical network admittance matrix properties. The admittance matrix methodology described in This work is rigorously validated by comparing the decoupling capacitor placement evaluation of a real printed circuit board by both impedance matrix and results from commercial electromagnetic field software.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"17 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125886067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Crosstalk-insensitive layout generation using artificial neural networks 基于人工神经网络的串扰不敏感布局生成
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407617
A. Ilumoka, T. Chen
{"title":"Crosstalk-insensitive layout generation using artificial neural networks","authors":"A. Ilumoka, T. Chen","doi":"10.1109/EPEP.2004.1407617","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407617","url":null,"abstract":"Crosstalk minimization is carried out on equivalent circuit models of interconnect layout using gradient-based optimization. Optimized SPICE parameters are then used to generate crosstalk-insensitive layouts by use of neural networks. Results obtained - verified by MOSIS fabrication - indicate that crosstalk noise reduction of up to 60% can be achieved with relatively small adjustments to interconnect layout geometry.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124698084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A method and tool set for on-chip power noise and jitter estimation 片上功率噪声和抖动估计的方法和工具集
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407571
R. J. Evans, K. Carlsen, A. Joshi
{"title":"A method and tool set for on-chip power noise and jitter estimation","authors":"R. J. Evans, K. Carlsen, A. Joshi","doi":"10.1109/EPEP.2004.1407571","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407571","url":null,"abstract":"This work describes a method for estimating on-die and package jitter noise for standard-cell ASICs. This method uses extractions of the physical layouts, with current consumption behavioral model estimations of core cells, to estimate the core voltage noise at various die locations. The resulting voltage and ground noise waveforms are then used as the voltage rail inputs for simulations of extracted signal nets to estimate their jitter due to this core noise. These voltage noise waveforms are then used as the supply inputs for simulating jitter on critical nets.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124799846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electromagnetic modeling as a constituent of multi-disciplined design 电磁建模作为多学科设计的组成部分
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407539
N. Buris
{"title":"Electromagnetic modeling as a constituent of multi-disciplined design","authors":"N. Buris","doi":"10.1109/EPEP.2004.1407539","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407539","url":null,"abstract":"A scalable framework of multi-disciplined design that is able to accommodate any geometric based design discipline is presented. Of the several challenges in the way of high fidelity, physics based design and modeling are the focus of This work. The complexity of a problem described in its raw geometry is overwhelming. The second challenge discussed in This work is the coupling of most, if not all disciplines in an optimization problem when described at the geometric level. Often, the degree of discipline coupling is a function of the type and level of optimization that one is \"willing\" to pursue, or ignore. Application examples are given in the area of electromagnetic and structural analyses for components appearing in cellular phones.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Block partitioned Gauss-Seidel PEEC solver accelerated by QR-based coupling matrix compression techniques 基于qr的耦合矩阵压缩技术加速块分割高斯-塞德尔PEEC求解
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407624
A. Ruehli, D. Gope, V. Jandhyala
{"title":"Block partitioned Gauss-Seidel PEEC solver accelerated by QR-based coupling matrix compression techniques","authors":"A. Ruehli, D. Gope, V. Jandhyala","doi":"10.1109/EPEP.2004.1407624","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407624","url":null,"abstract":"Electromagnetic (EM) integral equation solvers based on the partial element equivalent circuit (PEEC) approach have proven to be well suited for modeling combined circuit and EM problems. The solution of the full-wave electromagnetic part is transformed to the circuit domain and general well-known circuit solver techniques are applied. However owing to the mutual couplings in the PEEC formulation, the MNA matrix is not sparse as in the case of general lumped circuits. This gives rise to a time and memory bottleneck. A Gauss-Seidel relaxation (GSR) solver is presented as an appropriate alternative to SPICE sparse LU solvers, for the PEEC class of problems in the frequency domain. Circuit based block partitioning schemes similar to the ones used in waveform relaxation methods with known convergence properties are used to insure fast convergence. Furthermore, circuit coupling thinning schemes based on QR compression techniques are used to accelerate the inter block updates and also intra block solutions.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126417432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Expedient methodology for the quantification of interconnect-induced semiconductor substrate noise 互连感应半导体衬底噪声量化的权宜方法
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407607
I. Chung, A. Cangellaris
{"title":"Expedient methodology for the quantification of interconnect-induced semiconductor substrate noise","authors":"I. Chung, A. Cangellaris","doi":"10.1109/EPEP.2004.1407607","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407607","url":null,"abstract":"A methodology is proposed for the quantification and analysis of interconnect-induced noise in semiconductor substrates. The methodology is based on the utilization of commonly-used two-dimensional interconnect parasitics extractors together with SPICE-like simulators. Thus, the proposed model offers a convenient alternative to the use of three-dimensional field solvers for the expedient investigation of the attributes and potential consequences of interconnect-induced substrate noise on on-chip signal integrity.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128724509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power distribution analysis for IBM eServer system integration optimization IBM eServer系统集成优化的配电分析
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407581
A. Huber, T. Zhou, W. Becker, R. Weekly, E. Klink
{"title":"Power distribution analysis for IBM eServer system integration optimization","authors":"A. Huber, T. Zhou, W. Becker, R. Weekly, E. Klink","doi":"10.1109/EPEP.2004.1407581","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407581","url":null,"abstract":"Server system design is strongly influenced by power delivery aspects. Multiple requirements and limitations must be taken into consideration. This requires an appropriate DC analysis workflow. This contribution outlines a DC strategy used for IBM eServer design. The strategy is divided into two parts, PrePD and PostPD. PrePD type of analysis is used for system high-level design and optimization including parts selection, number of board layers, module sizing and placement on board, interface pin pattern optimization for both module to board and board to backplane. PostPD analysis is used for first level packaging design optimization and verification. The combination of PrePD and PostPD analysis serves as an efficient and useful tool, shown by the examples of various applications, for server power delivery system design.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121880714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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