基于人工神经网络的串扰不敏感布局生成

A. Ilumoka, T. Chen
{"title":"基于人工神经网络的串扰不敏感布局生成","authors":"A. Ilumoka, T. Chen","doi":"10.1109/EPEP.2004.1407617","DOIUrl":null,"url":null,"abstract":"Crosstalk minimization is carried out on equivalent circuit models of interconnect layout using gradient-based optimization. Optimized SPICE parameters are then used to generate crosstalk-insensitive layouts by use of neural networks. Results obtained - verified by MOSIS fabrication - indicate that crosstalk noise reduction of up to 60% can be achieved with relatively small adjustments to interconnect layout geometry.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"104 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Crosstalk-insensitive layout generation using artificial neural networks\",\"authors\":\"A. Ilumoka, T. Chen\",\"doi\":\"10.1109/EPEP.2004.1407617\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Crosstalk minimization is carried out on equivalent circuit models of interconnect layout using gradient-based optimization. Optimized SPICE parameters are then used to generate crosstalk-insensitive layouts by use of neural networks. Results obtained - verified by MOSIS fabrication - indicate that crosstalk noise reduction of up to 60% can be achieved with relatively small adjustments to interconnect layout geometry.\",\"PeriodicalId\":143349,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging - 2004\",\"volume\":\"104 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging - 2004\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2004.1407617\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging - 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2004.1407617","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

采用梯度优化方法对互连布线等效电路模型进行串扰最小化。优化SPICE参数,然后使用神经网络生成串扰不敏感布局。得到的结果-通过MOSIS制造验证-表明,通过相对较小的互连布局几何调整,可以实现高达60%的串扰噪声降低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Crosstalk-insensitive layout generation using artificial neural networks
Crosstalk minimization is carried out on equivalent circuit models of interconnect layout using gradient-based optimization. Optimized SPICE parameters are then used to generate crosstalk-insensitive layouts by use of neural networks. Results obtained - verified by MOSIS fabrication - indicate that crosstalk noise reduction of up to 60% can be achieved with relatively small adjustments to interconnect layout geometry.
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