A method and tool set for on-chip power noise and jitter estimation

Abstract

This work describes a method for estimating on-die and package jitter noise for standard-cell ASICs. This method uses extractions of the physical layouts, with current consumption behavioral model estimations of core cells, to estimate the core voltage noise at various die locations. The resulting voltage and ground noise waveforms are then used as the voltage rail inputs for simulations of extracted signal nets to estimate their jitter due to this core noise. These voltage noise waveforms are then used as the supply inputs for simulating jitter on critical nets.