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2017 IEEE East-West Design & Test Symposium (EWDTS)最新文献

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Periodic boundary cellular automata based test structure for memory 基于周期边界元胞自动机的记忆测试结构
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110050
M. Saha, B. Das, B. Sikdar
{"title":"Periodic boundary cellular automata based test structure for memory","authors":"M. Saha, B. Das, B. Sikdar","doi":"10.1109/EWDTS.2017.8110050","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110050","url":null,"abstract":"This work reports an effective test design for memory. It realizes March algorithm employing a periodic boundary cellular automata (PBCA) structure. The irreversible single length cycle attractor cellular automata (CA), selected for the design, returns correct decision on the fault in memory even if the test logic is defective. It avoids the bit by bit comparison of memory words, practiced in the conventional test designs, and outperforms the state-of-the-art memory test architecture in terms of delay in testing. The hardware overhead of CA based test design is insignificant in comparison to the cost of memory.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126932068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Search algorithm for fully tested elements in combinational circuits, controlled on the basis of berger codes 基于伯杰码控制的组合电路中完全测试元件的搜索算法
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110085
V. Sapozhnikov, V. Sapozhnikov, D. Efanov
{"title":"Search algorithm for fully tested elements in combinational circuits, controlled on the basis of berger codes","authors":"V. Sapozhnikov, V. Sapozhnikov, D. Efanov","doi":"10.1109/EWDTS.2017.8110085","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110085","url":null,"abstract":"Authors describe firstly obtained necessary and sufficient conditions for detection of a logic component output fault in the combination logic structure controlled on the basis of Berger code. It is demonstrated that for the solution of the given task not only Berger code property of identifying any unidirectional errors in data vectors, but also the property of any asymmetric errors detection may be applied. An algorithm of the analysis of logical elements testability was formed. Non-tested elements in the process of transforming a circuit into a circuit with testable structure should be reserved. On the basis of formed conditions of full testability of logical elements controlled by Berger code, the methods of network reduction may be developed, providing the decreased, compared to the existing methods, redundancy.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116573355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Simulation methods for load balancing in distributed computing 分布式计算中负载均衡的仿真方法
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110078
Igor Ivanisenko, Maksym Volk
{"title":"Simulation methods for load balancing in distributed computing","authors":"Igor Ivanisenko, Maksym Volk","doi":"10.1109/EWDTS.2017.8110078","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110078","url":null,"abstract":"The paper proposes the solution of the actual scientific problem of load balancing and efficient use of distributed system resources. The proposed method is based on the calculation of the load of the central processor, memory and bandwidth fractal information streams of different classes of service for each server and the entire distributed system. The method allows calculating the imbalance of all system servers and use of the system. In general, Simulation modeling of the proposed method for various multi-fractal parameters of input streams have been carried out, which showed that the characteristics of multi-fractal traffic noticeably affect the system imbalance. The use of the proposed method allows for higher performance of the system and faster flow processing.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133626053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PHP: Power hungry pattern generation at higher abstraction level PHP:在更高抽象级别生成耗电模式
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110061
Rohini Gulve, Anshu Goel, Virendra Singh
{"title":"PHP: Power hungry pattern generation at higher abstraction level","authors":"Rohini Gulve, Anshu Goel, Virendra Singh","doi":"10.1109/EWDTS.2017.8110061","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110061","url":null,"abstract":"The Performance, area, and power are most essential factors to be considered and optimize at every step in the design cycle. Design engineers often need to learn about these factors in order make right decisions on design strategies. Power analysis at lower levels of abstraction can provide more accurate analysis than higher levels. Worst case power can be estimated through high activity pattern generation. However, generation of such power hungry patterns (PHP) become challenging as the number of modules or design components increases. This process can be accelerated at higher abstraction levels by utilizing the available information. In this paper, we generate PHP by at higher abstraction level with significant speed up. A genetic algorithm is implemented to find out the global maximum power of designs. An experiment indicates that the process implemented is much faster and it finds about 10 % more power demanding PHP than random samples generated.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"356 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133969463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Recursive identification of bilinear dynamical systems with noise in output signal 输出信号中有噪声的双线性动力系统的递归辨识
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110066
Dmitriy Ivanov, E. U. Bobkova, A. Zharkova
{"title":"Recursive identification of bilinear dynamical systems with noise in output signal","authors":"Dmitriy Ivanov, E. U. Bobkova, A. Zharkova","doi":"10.1109/EWDTS.2017.8110066","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110066","url":null,"abstract":"A recursive algorithm is proposed for identification single-input-single-output bilinear dynamic systems with output-error. The estimates are proved to be convergent to the true values almost surely (a.s.). The results of a simulated example show that the accuracy of the proposed algorithm is higher than that of recursive least square and recursive extended instrumental variables algorithms.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of application specific instruction-set processor for the artificial neural network acceleration using LISA ADL 利用LISA ADL实现应用特定指令集处理器的人工神经网络加速
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110039
Damjan Rakanovic, R. Struharik
{"title":"Implementation of application specific instruction-set processor for the artificial neural network acceleration using LISA ADL","authors":"Damjan Rakanovic, R. Struharik","doi":"10.1109/EWDTS.2017.8110039","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110039","url":null,"abstract":"In fields like embedded vision, where algorithms are computationally expensive, hardware accelerators play a major role in high throughput applications. These accelerators could be implemented as hardwired IP cores or Application Specific Instruction-set Processors (ASIPs). While hardwired solutions often provide the best possible performance, they are less flexible then ASIP implementation. In this paper, we present a design flow of ASIP for feed-forward fully-connected neural network acceleration. Design was named Neural Network ASIP (NNAP) and developed using LISA language for ASIP, tested on Zynq7020 FPGA and finally, its performance was compared to the software solution running on the ARM Cortex-A9 core. It was shown that the performance of ASIP solution, running on Zynq FPGA, is approximately from 20 to 40 times faster when compared to the software implementation, running on the ARM based architecture.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115293735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cloud-driven trafile control: Route service metric 云驱动的流量控制:路由服务度量
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110153
Artur Ziarmand, E. Litvinova, S. Chumachenko, V. Hahanov
{"title":"Cloud-driven trafile control: Route service metric","authors":"Artur Ziarmand, E. Litvinova, S. Chumachenko, V. Hahanov","doi":"10.1109/EWDTS.2017.8110153","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110153","url":null,"abstract":"The cloud-driven traffic control and road service metric for searching the optimal route on the road infrastructure between two coordinates, which are identified with the point of departure and arrival, is considered. Possible restrictions are related to road collisions, accidents and road repairs, which is taken into account when choosing the best route. The method is implemented in the online cloud service for vehicle drivers as part of a cyber-transportation system for intelligent cloud automotive control. We propose a triangular road infrastructure and quality criterion of the infrastructure, taking into account the sums of routs between node pairs of the topology graph reduced to the number of edges.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124755979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A complementary LC-tank based IR-UWB pulse generator for BPSK modulation 用于BPSK调制的互补LC-tank型IR-UWB脉冲发生器
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110138
I. Kianpour, Bilal Hussain, V. Tavares
{"title":"A complementary LC-tank based IR-UWB pulse generator for BPSK modulation","authors":"I. Kianpour, Bilal Hussain, V. Tavares","doi":"10.1109/EWDTS.2017.8110138","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110138","url":null,"abstract":"This paper presents a low-power binary phase shift keying (BPSK) pulse generator for ultra-wide-band transmitters. The circuit has been designed based on LC-tank resonators using 0.13 um CMOS technology. Simulation shows −10dB bandwidth of around 3 GHz and power consumption of 2 mW at 100 MHz PRF. Peak-peak amplitude voltage for both symbols ‘1’ and ‘0’ are approximately as large as 1.2V supply voltage and can radiate enough energy to satisfy the FCC mask only by one pulse. Thus, the energy consumption is 20 pJ/pulse/bit. Pulse duration is 1.5 ns and the transmitter can reach data rates of 660 Mbps.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"31 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124840400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New technology in sphere of diagnostic information transfer within monitoring system of transportation and industry 运输和工业监测系统中诊断信息传递领域的新技术
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110152
D. Efanov, G. Osadchy, D. Sedykh, Dmitry Pristensky, Igor Razvitnov, Pyotr Skurlov
{"title":"New technology in sphere of diagnostic information transfer within monitoring system of transportation and industry","authors":"D. Efanov, G. Osadchy, D. Sedykh, Dmitry Pristensky, Igor Razvitnov, Pyotr Skurlov","doi":"10.1109/EWDTS.2017.8110152","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110152","url":null,"abstract":"The problem of industrial network application for the purpose of data transfer within permanent monitoring systems is being analyzed. This task is considered as essential within systems of critical action, for example transportation systems. Authors in present article suggest the new option on network arrangement and compare it with famous network “Lo-RaWAN” together with data regarding developed by authors network of data transfer with personalized protocol, which helps to optimize the terms of service. Also, some features are being indicated reckoning network arranged on speedy railway test site “St. Petersburg — Moscow”, Russian Federation.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122943314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Experimental study on Hamming and Hsiao codes in the context of embedded applications 嵌入式应用环境下汉明码和萧码的实验研究
2017 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2017-09-01 DOI: 10.1109/EWDTS.2017.8110065
Grigor Tshagharyan, Gurgen Harutunyan, S. Shoukourian, Y. Zorian
{"title":"Experimental study on Hamming and Hsiao codes in the context of embedded applications","authors":"Grigor Tshagharyan, Gurgen Harutunyan, S. Shoukourian, Y. Zorian","doi":"10.1109/EWDTS.2017.8110065","DOIUrl":"https://doi.org/10.1109/EWDTS.2017.8110065","url":null,"abstract":"Increasing soft error rate and decreasing technological nodes sizes pave a way for Error Correcting Codes (ECC) widespread use in embedded systems. Depending on application safety goals and acceptable performance and area overhead, different codes can be selected. The goal of this paper is to investigate the efficiency and expediency of two of the most prominent ECC codes, Hamming and Hsiao, in the context of embedded memories and provide practical guidance for their exploitation.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123025988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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