{"title":"基于伯杰码控制的组合电路中完全测试元件的搜索算法","authors":"V. Sapozhnikov, V. Sapozhnikov, D. Efanov","doi":"10.1109/EWDTS.2017.8110085","DOIUrl":null,"url":null,"abstract":"Authors describe firstly obtained necessary and sufficient conditions for detection of a logic component output fault in the combination logic structure controlled on the basis of Berger code. It is demonstrated that for the solution of the given task not only Berger code property of identifying any unidirectional errors in data vectors, but also the property of any asymmetric errors detection may be applied. An algorithm of the analysis of logical elements testability was formed. Non-tested elements in the process of transforming a circuit into a circuit with testable structure should be reserved. On the basis of formed conditions of full testability of logical elements controlled by Berger code, the methods of network reduction may be developed, providing the decreased, compared to the existing methods, redundancy.","PeriodicalId":141333,"journal":{"name":"2017 IEEE East-West Design & Test Symposium (EWDTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Search algorithm for fully tested elements in combinational circuits, controlled on the basis of berger codes\",\"authors\":\"V. Sapozhnikov, V. Sapozhnikov, D. Efanov\",\"doi\":\"10.1109/EWDTS.2017.8110085\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Authors describe firstly obtained necessary and sufficient conditions for detection of a logic component output fault in the combination logic structure controlled on the basis of Berger code. It is demonstrated that for the solution of the given task not only Berger code property of identifying any unidirectional errors in data vectors, but also the property of any asymmetric errors detection may be applied. An algorithm of the analysis of logical elements testability was formed. Non-tested elements in the process of transforming a circuit into a circuit with testable structure should be reserved. On the basis of formed conditions of full testability of logical elements controlled by Berger code, the methods of network reduction may be developed, providing the decreased, compared to the existing methods, redundancy.\",\"PeriodicalId\":141333,\"journal\":{\"name\":\"2017 IEEE East-West Design & Test Symposium (EWDTS)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2017.8110085\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2017.8110085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Search algorithm for fully tested elements in combinational circuits, controlled on the basis of berger codes
Authors describe firstly obtained necessary and sufficient conditions for detection of a logic component output fault in the combination logic structure controlled on the basis of Berger code. It is demonstrated that for the solution of the given task not only Berger code property of identifying any unidirectional errors in data vectors, but also the property of any asymmetric errors detection may be applied. An algorithm of the analysis of logical elements testability was formed. Non-tested elements in the process of transforming a circuit into a circuit with testable structure should be reserved. On the basis of formed conditions of full testability of logical elements controlled by Berger code, the methods of network reduction may be developed, providing the decreased, compared to the existing methods, redundancy.