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2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers最新文献

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A 10 Gbit/s switch matrix MMIC using InP HEMTs with a logic-level-independent interface 采用InP hemt的10gbit /s开关矩阵MMIC，具有逻辑电平独立接口
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320610
H. Kamitsuna, H. Kitabayashi, H. Matsuzaki, M. Tokumitsu, M. Muraguchi
{"title":"A 10 Gbit/s switch matrix MMIC using InP HEMTs with a logic-level-independent interface","authors":"H. Kamitsuna, H. Kitabayashi, H. Matsuzaki, M. Tokumitsu, M. Muraguchi","doi":"10.1109/RFIC.2004.1320610","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320610","url":null,"abstract":"An InP HEMT with a low on-resistance /spl times/ off-capacitance (Ron /spl times/ Coff) product enables us to configure a dc-to-over-10 GHz switch without using a shunt FET. The series FET configuration makes possible control-voltage-polarity independence, and offers a logic-level-independent interface. A 2/spl times/2 switch matrix MMIC yields an insertion loss of less than 1.16 dB and an isolation of more than 21.2 dB below 10 GHz. The MMIC also achieves error-free switch matrix operation up to 12.5 Gbit/s, using either a source coupled FET logic SCFL (1 V/sub p-p/, dc offset: -0.5 V) or low voltage differential signalling LVDS (0.3 V/sub p-p/, dc offset: +1.2 V) level.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125490308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 4.92-5.845 GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN 用于IEEE 802.11a无线局域网的4.92-5.845 GHz直接转换CMOS收发器
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320614
A. Behzad, E. Lin, K. Carter, M. Kappes, Z.M. Shi, L. Lin, S. Wu, S. Anand, T. Nguyen, D. Yuan, Y. C. Wong, V. Fong, B. Yeung, A. Rofougaran
{"title":"A 4.92-5.845 GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN","authors":"A. Behzad, E. Lin, K. Carter, M. Kappes, Z.M. Shi, L. Lin, S. Wu, S. Anand, T. Nguyen, D. Yuan, Y. C. Wong, V. Fong, B. Yeung, A. Rofougaran","doi":"10.1109/RFIC.2004.1320614","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320614","url":null,"abstract":"A fully integrated CMOS direct-conversion 5 GHz transceiver is implemented in a 0.18 /spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution covering all of the world-wide 4.92-5.845 GHz bands. The receiver achieves a 3.5 dB NF while the transmitter achieves a +23 dBm saturated output power. The integrated PA utilizes a linearization technique to allow for high efficiency while maintaining the linear operation required by QAM64 OFDM signals. The transceiver achieves low cost and high yield through the use of various integrated self-contained or system level calibration techniques.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131820491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
TDC-based frequency synthesizer for wireless applications 无线应用的基于tdc的频率合成器
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320575
R. Staszewski, Dirk K I P O L D, C. Hung, P. Balsara
{"title":"TDC-based frequency synthesizer for wireless applications","authors":"R. Staszewski, Dirk K I P O L D, C. Hung, P. Balsara","doi":"10.1109/RFIC.2004.1320575","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320575","url":null,"abstract":"We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous over conventional charge-pump-based PLL, since it contains only two intrinsic phase noise sources and it does not rely on the fine voltage resolution of analog circuits. The measured close-in phase noise of -86.2 dBc/Hz and the rms phase error of 0.9/spl deg/ are adequate also for GSM applications.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133624911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
Broadband compact models for transformers integrated on conductive silicon substrates 宽带紧凑型变压器集成在导电硅衬底
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320652
T. Kamgaing, M. Petras, M. Miller
{"title":"Broadband compact models for transformers integrated on conductive silicon substrates","authors":"T. Kamgaing, M. Petras, M. Miller","doi":"10.1109/RFIC.2004.1320652","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320652","url":null,"abstract":"A broadband scalable lumped-element model for multiport transformers integrated on a silicon substrate is presented. The model is based on a pi-T network for the primary and secondary coils and utilizes only frequency-independent elements to model the frequency-dependent resistive losses. Four-port S-parameters are measured for multiport transformers up to 15 GHz and accurate compact models extracted up to 4 GHz, which covers the fundamental frequency bands and their second harmonics of interest for European and US GSM/EGSM and DCS/PCS cellular bands. Good agreement is obtained between modeled and measured transformer performance attributes.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132290634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Trap wave method for high isolation series RF MEMS switches application 陷波法在高隔离串联RF MEMS开关中的应用
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320588
H. Gu, B. Gao
{"title":"Trap wave method for high isolation series RF MEMS switches application","authors":"H. Gu, B. Gao","doi":"10.1109/RFIC.2004.1320588","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320588","url":null,"abstract":"This paper presents a trap wave circuit structure to compensate for the coupled capacitance, to increase the switch isolation. The switch is first accurately modeled using numerical and experimental techniques, and its equivalent capacitance model is derived, then the comb capacitance-spiral inductance trap wave circuit is derived using RF circuit simulation software. The layout of the structure can be realized with no extra fabrication processes. Theoretical analysis shows that the isolation can be improved by 15.6 dB, but the insertion loss is only affected by 0.07 dB, in the frequency range from 2-5 GHz, when this method is applied.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver 低中频接收机的共模电压和差分偏置电压联合控制方案
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320636
K. Muhammad, R. Staszewski, C. Hung
{"title":"Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver","authors":"K. Muhammad, R. Staszewski, C. Hung","doi":"10.1109/RFIC.2004.1320636","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320636","url":null,"abstract":"Direct RF sampling has recently been presented (K. Muhammad et al., Proc. IEEE Solid-State Circ. Conf, sec. 15.1, pp. 268-269, 527, 2004; K. Muhammad and R.B. Staszewski, Proc. IEEE Intl. Symp. on Circ. and Sys., sec. ASP-L29.5, 2004) in which an input RF signal is converted to current waveform, down-converted and integrated on a sampling capacitor. A rotating capacitor shares this charge with the sampling capacitor and transfers it to a subsequent discrete time switched-capacitor filter stage. In this paper, we present a mixed-signal approach for controlling the common mode voltage as well as injecting differential charge to compensate for the DC-offsets. This approach has been validated and incorporated in a commercial Bluetooth receiver IC realized in a digital 130 nm CMOS technology that meets or exceeds performance of other conventional Bluetooth radio architectures.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114590077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A multiphase PLL for 10 Gb/s links in SOI CMOS technology 基于SOI CMOS技术的10gb /s链路多相锁相环
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320573
M. Kossel, T. Morf, W. Baumberger, A. Biber, C. Menolfi, Thomas, T Toifl, M. Schmatz
{"title":"A multiphase PLL for 10 Gb/s links in SOI CMOS technology","authors":"M. Kossel, T. Morf, W. Baumberger, A. Biber, C. Menolfi, Thomas, T Toifl, M. Schmatz","doi":"10.1109/RFIC.2004.1320573","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320573","url":null,"abstract":"This paper presents a multiphase PLL designed for a 10/spl times/10 Gbit/s serial link bundle that is based on a digital CDR receiver. The PLL was fabricated in a 90-nm SOI CMOS process and covers a frequency band of 9.6-12.8 GHz at a supply voltage of 1.7 V. Measurement results showed a peak-to-peak jitter of less than 0.12 UI and a power consumption efficiency of 1.5 mW/GHz per link.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117326808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A SiGe differential active filter using a Sallen and Key cell 一种SiGe差分有源滤波器，采用Sallen和Key单元
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320705
F. Temcamani, H. Diab, M. Regis, J. Gautier
{"title":"A SiGe differential active filter using a Sallen and Key cell","authors":"F. Temcamani, H. Diab, M. Regis, J. Gautier","doi":"10.1109/RFIC.2004.1320705","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320705","url":null,"abstract":"In this paper, a 1.3 GHz band pass filter, based on a Sallen and Key cell, is presented. A new amplifier topology of the S-K cell is proposed, with input and output differential amplifiers optimized to have high performances in terms of CMMR, IP3 and noise figure. All the filter stages were realized with a SiGe BiCMOS technology. Comparison showed a good agreement between simulation and measurements. In particular, the S-K amplifier gain and the filter selectivity can be tuned. Q factors of up to 60 were measured. The measured even-mode rejection is close to 30 dB at the center frequency.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116824381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of buried layers doping rate on substrate noise coupling: efficiency of deep-trench techniques to improve isolation capability 埋层掺杂率对衬底噪声耦合的影响:深沟技术提高隔离性能的效率
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320563
S. Wane, D. Bajon, H. Baudrand, C. Biard, J. Langanay, P. Gamand
{"title":"Effects of buried layers doping rate on substrate noise coupling: efficiency of deep-trench techniques to improve isolation capability","authors":"S. Wane, D. Bajon, H. Baudrand, C. Biard, J. Langanay, P. Gamand","doi":"10.1109/RFIC.2004.1320563","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320563","url":null,"abstract":"In this paper a full wave investigation of the dependence of substrate noise coupling and of deep-trench techniques efficiency on buried epitaxial layers doping rates is presented. Different grounding configurations for the buried epitaxial layers are considered to estimate the impact of spatial distribution of ground contacts on the global isolation performance between sensitive blocks. Single and double oxide deep-trenches are introduced to reduce substrate noise coupling and demonstrate significant isolation capability. Simulation results obtained using a home made simulator are successfully compared to published measurements and to commercial design tools.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125901476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme 采用减小尺寸分布式保护方案的宽带射频电路ESD保护设计
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers Pub Date : 2004-06-06 DOI: 10.1109/RFIC.2004.1320629
M. Ker, B. Kuo
{"title":"ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme","authors":"M. Ker, B. Kuo","doi":"10.1109/RFIC.2004.1320629","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320629","url":null,"abstract":"The resulting capacitive load, from a large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broadband RF circuits due to the impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme, using equal four-stage ESD protection can achieve a better impedance match, but degrades the ESD performance. A new distributed ESD protection structure is proposed in this work, to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, named decreasing-size distributed ESD (DS-DESD) protection scheme, which is beneficial to the ESD level. The experimental results have shown a human-body-model (HBM) ESD robustness of up to 8 kV.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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