M. Kossel, T. Morf, W. Baumberger, A. Biber, C. Menolfi, Thomas, T Toifl, M. Schmatz
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引用次数: 6
摘要
本文提出了一种基于数字CDR接收机的用于10/spl倍/ 10gbit /s串行链路束的多相锁相环。该锁相环采用90nm SOI CMOS工艺制备，在1.7 V电源电压下覆盖9.6-12.8 GHz频段。测量结果表明，峰间抖动小于0.12 UI，每链路功耗效率为1.5 mW/GHz。
A multiphase PLL for 10 Gb/s links in SOI CMOS technology
This paper presents a multiphase PLL designed for a 10/spl times/10 Gbit/s serial link bundle that is based on a digital CDR receiver. The PLL was fabricated in a 90-nm SOI CMOS process and covers a frequency band of 9.6-12.8 GHz at a supply voltage of 1.7 V. Measurement results showed a peak-to-peak jitter of less than 0.12 UI and a power consumption efficiency of 1.5 mW/GHz per link.
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