H. Kamitsuna, H. Kitabayashi, H. Matsuzaki, M. Tokumitsu, M. Muraguchi
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A 10 Gbit/s switch matrix MMIC using InP HEMTs with a logic-level-independent interface
An InP HEMT with a low on-resistance /spl times/ off-capacitance (Ron /spl times/ Coff) product enables us to configure a dc-to-over-10 GHz switch without using a shunt FET. The series FET configuration makes possible control-voltage-polarity independence, and offers a logic-level-independent interface. A 2/spl times/2 switch matrix MMIC yields an insertion loss of less than 1.16 dB and an isolation of more than 21.2 dB below 10 GHz. The MMIC also achieves error-free switch matrix operation up to 12.5 Gbit/s, using either a source coupled FET logic SCFL (1 V/sub p-p/, dc offset: -0.5 V) or low voltage differential signalling LVDS (0.3 V/sub p-p/, dc offset: +1.2 V) level.
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