A multiphase PLL for 10 Gb/s links in SOI CMOS technology

Abstract

This paper presents a multiphase PLL designed for a 10/spl times/10 Gbit/s serial link bundle that is based on a digital CDR receiver. The PLL was fabricated in a 90-nm SOI CMOS process and covers a frequency band of 9.6-12.8 GHz at a supply voltage of 1.7 V. Measurement results showed a peak-to-peak jitter of less than 0.12 UI and a power consumption efficiency of 1.5 mW/GHz per link.