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2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)最新文献

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High Signal Integrity Transmission Line Using Microchip Capacitors and Inductors 采用微芯片电容器和电感的高信号完整性传输线
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312898
Takahiko Kano, M. Yasunaga
{"title":"High Signal Integrity Transmission Line Using Microchip Capacitors and Inductors","authors":"Takahiko Kano, M. Yasunaga","doi":"10.1109/EDAPS50281.2020.9312898","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312898","url":null,"abstract":"In order to improve signal integrity (SI) in PCB traces, or transmission lines, impedance matching techniques have been widely used so far. However, in the frequency domain of more than 5 GHz, it becomes difficult to make impedance matching designs in printed circuit boards (PCBs). In this paper, we propose a novel trace structure called \"Capacitor Inductor Segmental Transmission Line (CL-STL)\", in which not impedance matching but \"mismatching\" is used to improve SI. In the CL-STL, microchip capacitors and inductors are connected to the transmission line to make impedance mismatching points and to generate reflection waves intentionally, and those reflection waves are superposed onto the original distorted wave to get it into shape. In the CL-STL design, we make use of the cuckoo search algorithm, which is one of the swarm intelligence optimization algorithms, to solve the combinatorial explosion problem of microchip capacitors and inductors. We apply the CL-STL to an 8 Gbps PCB trace and obtain a high SI eye-diagram, the height and the width of which are improved by 6.9 and 1.44 times, respectively.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133218591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gaussian Process surrogate model for variability analysis of RF circuits 射频电路变异性分析的高斯过程替代模型
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312886
Thong Nguyen, J. Schutt-Ainé
{"title":"Gaussian Process surrogate model for variability analysis of RF circuits","authors":"Thong Nguyen, J. Schutt-Ainé","doi":"10.1109/EDAPS50281.2020.9312886","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312886","url":null,"abstract":"Non-intrusive methods for studying processes involving variables changing such as design optimization, manufacture variation etc. require evaluations of the quantity of interests for a numerous times. These methods, hence, rely on an accurate surrogate model of the process under study. Gaussian Process (GP) is a well-known non-parametric modeling technique for surrogate modeling. This paper explores the effectiveness of GP to model RF applications. The analysis of a milimeter-wave bandpass filter is presented to illustrate the method.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114062725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power Delivery Network Design and Optimization for Ethernet I/O 以太网I/O供电网络设计与优化
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312901
Siri Holla, M. Moorthy, Manjunath Jayasimha
{"title":"Power Delivery Network Design and Optimization for Ethernet I/O","authors":"Siri Holla, M. Moorthy, Manjunath Jayasimha","doi":"10.1109/EDAPS50281.2020.9312901","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312901","url":null,"abstract":"As the High-speed IO & Ethernet data rate is increasing, meeting the Power integrity specifications at the die, package & board is becoming highly challenging. With Data Centre servers having multiple SERDES interfaces of 56G Ethernet protocol, it has become very critical to find the solution to meet the stringent noise spec with reduced BOM cost and meet noise coupling requirements due to power management states of PHY. Power supply noise has been scaling to lower value to meet PSIJ (power supply induced Jitter) adds more complexity of the solution. Due to limitation of BOM cost, power & requirements for high performance, detailed understanding on source of power supply noise in the system has become necessary. This Paper deals with the solution & analysis of power Supply noise looking towards die, package & board with tightly integrated multiple 56G Ethernet Phys.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123702015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of Different Learning Methods for the Modelling of Microstrip Characteristics 不同学习方法在微带特性建模中的应用
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312887
N. Soleimani, R. Trinchero, F. Canavero
{"title":"Application of Different Learning Methods for the Modelling of Microstrip Characteristics","authors":"N. Soleimani, R. Trinchero, F. Canavero","doi":"10.1109/EDAPS50281.2020.9312887","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312887","url":null,"abstract":"In this paper, the performance of four machine learning regressions like Support Vector Machine (SVM), Least Square-Support Vector Machine (LS-SVM), Gaussian Process Regression (GPR) and Random Forest method (RF) are investigated by means of an illustrative example referring to the characteristic impedance of a microstrip line in terms of electrical and geometrical parameters. The required dataset for training is obtained from a set of parametric electromagnetic simulations. The performance comparison of the four methods is done in the presence and absence of numerical noise and inaccuracies affecting the training samples. The results of our comparison provide a guidance for the proper method selection to model the electromagnetic characteristics of interconnects for high-speed signals: advantages and drawbacks of each of the proposed techniques clearly emerge from this analysis.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127806337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
[EDAPS 2020 Front cover] [EDAPS 2020封面]
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/edaps50281.2020.9312914
{"title":"[EDAPS 2020 Front cover]","authors":"","doi":"10.1109/edaps50281.2020.9312914","DOIUrl":"https://doi.org/10.1109/edaps50281.2020.9312914","url":null,"abstract":"","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116468869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Divide by Two Injection-Locked Frequency Divider Using 3-D Inductive Mutual-Coupling 采用三维电感互耦，分频器分为两个注入锁定分频器
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312893
W. Lai, S. Jang
{"title":"Divide by Two Injection-Locked Frequency Divider Using 3-D Inductive Mutual-Coupling","authors":"W. Lai, S. Jang","doi":"10.1109/EDAPS50281.2020.9312893","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312893","url":null,"abstract":"The article designs a high-performance wide-band injection locked frequency divider by 2 (ILFD ÷2) from tsmc 0.18 μm CMOS technology. The ILFD proposes 3-D transformer-coupled resonator with two resonant frequencies. The ILFD can operate in three modes with overlapped locking ranges. The optimal bias condition yields wide locking range during low power with high figure of merit. The locking range is 3.3 GHz at 1.83 mW from 2.3 to 5.6 GHz.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132011052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Hexa-band Gysel Power Divider for Microwave Applications 用于微波应用的六波段陀螺功率分配器
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312917
Aijaz M. Zaidi, J. Kishor, M. Beg, B. Kanaujia, K. Rambabu
{"title":"A Hexa-band Gysel Power Divider for Microwave Applications","authors":"Aijaz M. Zaidi, J. Kishor, M. Beg, B. Kanaujia, K. Rambabu","doi":"10.1109/EDAPS50281.2020.9312917","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312917","url":null,"abstract":"This paper presents a hexa-band Gysel power divider (GPD) for microwave applications. By replacing each ʎ/4 transmission line (TL) of the conventional GPD by the hexa-band ʎ/4 TL the proposed GPD has been developed. In order to verify the approach, a hexa-band GPD has been developed on Printed Circuit Board (PCB) for f1 = Long Term Evolution (LTE) 0.7GHz, f2 = LTE1.7GHz, f3 = LTE2.6GHz, f4 = 3.9GHz, f5 = Public Safety Band 4.9GHz and f6 = Wireless Local Area Network (WLAN) 5.8GHz wireless applications and tested. Return loss and isolation better than 13dB has been obtained while preserving the transmission 3.5dB for all the six bands. The first time a hexa-band GPD has been developed.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"812 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129391037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performances of a Low Power Latch due to PSN PSN低功率锁存器的性能研究
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312907
Mithilesh Kumar, A. Majumder, Abir J. Mondal
{"title":"Performances of a Low Power Latch due to PSN","authors":"Mithilesh Kumar, A. Majumder, Abir J. Mondal","doi":"10.1109/EDAPS50281.2020.9312907","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312907","url":null,"abstract":"This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122560976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Communication Distance Enhancement of Transmission Line Coupler by Using Parallelized Driver ICs 利用并行驱动ic提高传输线耦合器的通信距离
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312888
Yamato Toyoda, M. Hamada, T. Kuroda
{"title":"Communication Distance Enhancement of Transmission Line Coupler by Using Parallelized Driver ICs","authors":"Yamato Toyoda, M. Hamada, T. Kuroda","doi":"10.1109/EDAPS50281.2020.9312888","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312888","url":null,"abstract":"Non-contact communication can be realized by using a transmission line coupler. A highly durable system can be created by using contactless communication. The transmission line coupler has a trade-off relationship between long-distance transmission and compact packaging, which is an implementation issue. In this paper, we have developed a system that doubles the transmission power by parallelizing the driver ICs and achieves both compact packaging and communication distance enhancement.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117008290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effective Segmentation approach of Package-to-PCB modeling using Full-Wave EM field Solver 全波电磁场求解器在封装到pcb建模中的有效分割方法
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2020-12-14 DOI: 10.1109/EDAPS50281.2020.9312900
H. Dsilva, Abhishek Jain, Sasikala J, Amit Kumar
{"title":"Effective Segmentation approach of Package-to-PCB modeling using Full-Wave EM field Solver","authors":"H. Dsilva, Abhishek Jain, Sasikala J, Amit Kumar","doi":"10.1109/EDAPS50281.2020.9312900","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312900","url":null,"abstract":"Today’s design of high data rate (25 Gbps+) channel calls out modeling of the package to printed circuit board interface using full-wave electromagnetic field solvers. The interaction of the package ball grid array and printed circuit board pad along with via to trace routing leads to an impedance discontinuity, which needs to be modeled given sensitivity of channel performance to reflections at high data rates. There is a need to break the package-to-PCB full model into segments as the use of full-wave electromagnetic field solvers are limited by available computational resources & simulation time. This work explores the package to printed circuit board modeling using full-wave electromagnetic field solver through the segmentation approach. Presented are results on placement of reference planes at different locations in creating segments and then cascading using S-parameters. Results through insertion loss, return loss, crosstalk and time domain reflectometry are shown in comparing the results of the segmentation approach with that of the full model using electromagnetic field solver. This effort is an attempt at presenting a valid approach at placement of reference planes through the segmentation approach using full-wave electromagnetic field solver for high speed package-to-PCB modeling.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126866554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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