{"title":"PSN低功率锁存器的性能研究","authors":"Mithilesh Kumar, A. Majumder, Abir J. Mondal","doi":"10.1109/EDAPS50281.2020.9312907","DOIUrl":null,"url":null,"abstract":"This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Performances of a Low Power Latch due to PSN\",\"authors\":\"Mithilesh Kumar, A. Majumder, Abir J. Mondal\",\"doi\":\"10.1109/EDAPS50281.2020.9312907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.\",\"PeriodicalId\":137699,\"journal\":{\"name\":\"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"volume\":\"115 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS50281.2020.9312907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS50281.2020.9312907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.
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