Power Delivery Network Design and Optimization for Ethernet I/O

Abstract

As the High-speed IO & Ethernet data rate is increasing, meeting the Power integrity specifications at the die, package & board is becoming highly challenging. With Data Centre servers having multiple SERDES interfaces of 56G Ethernet protocol, it has become very critical to find the solution to meet the stringent noise spec with reduced BOM cost and meet noise coupling requirements due to power management states of PHY. Power supply noise has been scaling to lower value to meet PSIJ (power supply induced Jitter) adds more complexity of the solution. Due to limitation of BOM cost, power & requirements for high performance, detailed understanding on source of power supply noise in the system has become necessary. This Paper deals with the solution & analysis of power Supply noise looking towards die, package & board with tightly integrated multiple 56G Ethernet Phys.