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2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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Employing incremental sigma delta DACs for high resolution SAR ADC 采用增量式σ δ ADC实现高分辨率SAR ADC
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049939
Ahmad AlMarashli, J. Anders, M. Ortmanns
{"title":"Employing incremental sigma delta DACs for high resolution SAR ADC","authors":"Ahmad AlMarashli, J. Anders, M. Ortmanns","doi":"10.1109/ICECS.2014.7049939","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049939","url":null,"abstract":"Successive Approximation Register analog-to-digital converters (SAR ADC) have received increasing attention due to their direct benefit from technology scaling. However, while the achievable speed has been improved significantly, the reported effective resolutions are usually limited below 12 bits. This is mostly caused by the limited accuracy of the common implementation of the internal digital-to-analog converter (DAC) as charge redistribution switched-capacitor DAC. To remove this limitation, this paper proposes a novel approach to build the internal DAC in a SAR ADC as an incremental Sigma-Delta modulator (SDM). With its simple and low cost design the proposed scheme for the feedback DAC enables the design of power and cost efficient, high resolution SAR ADCs. The proposed DAC incorporates an incremental digital SDM followed by a semi-digital reconstruction filter, which approximates the ideal reconstruction filter for a third order digital SDM, with relaxed matching requirements. The proposed architecture is compared to other common high resolution ADC topologies.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115903025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low noise CMOS image sensor with a 14-bit two-step single-slope ADC and a column self-calibration technique 一种低噪声CMOS图像传感器，具有14位两步单斜率ADC和柱自校准技术
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049918
Woongtaek Lim, Jongyoon Hwang, Dongjoo Kim, Shiwon Jeon, Suho Son, Minkyu Song
{"title":"A low noise CMOS image sensor with a 14-bit two-step single-slope ADC and a column self-calibration technique","authors":"Woongtaek Lim, Jongyoon Hwang, Dongjoo Kim, Shiwon Jeon, Suho Son, Minkyu Song","doi":"10.1109/ICECS.2014.7049918","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049918","url":null,"abstract":"In this paper, a low-noise CMOS Image Sensor (CIS) based on a 14-bit Two-Step Single-Slope ADC (TS SS ADC) and a column self-calibration technique is proposed. The TS SS ADC is good for the video system which requires fast operation because its conversion speed is faster than the Single Slope ADC (SS ADC) by more than 10 times. However, there are a lot of errors in the circuit operation on the connection point between the coarse block and the fine block due to the 2-step composition of the TS SS ADC. This makes it difficult to implement the TS SS ADC into the high resolution more than 10-bit and the product. In order to improve the drawbacks of TS SS ADC, a new 4-input comparator is discussed. Further, a column self-calibration technique to reduce the Fixed Pattern Noise (FPN) is also described. The chip has been fabricated by Samsung 0.13μm CIS technology. The measured conversion time of the ADC is 17μs and the high frame rate of 120 frames/s (fps) is achieved at the VGA resolution. The measured column FPN is 0.38LSB, and it is much lower than the other reported ones.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124178693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
80 GHz co-designed LNA and antenna for automotive radar 80ghz汽车雷达联合设计LNA和天线
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050038
Nicolas Martin, T. Taris, J. Bégueret, C. Person, D. Belot
{"title":"80 GHz co-designed LNA and antenna for automotive radar","authors":"Nicolas Martin, T. Taris, J. Bégueret, C. Person, D. Belot","doi":"10.1109/ICECS.2014.7050038","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050038","url":null,"abstract":"Co-designed Low Noise Amplifier (LNA) and dipole antenna in a RadioFrequency (RF) dedicated silicon technology, BÌCMOS9MW, are presented in this paper. The LNA is a two-stages cascode based on a SiGe:C 130 nm HBT optimized for maximum gain. The antenna is a dipole designed to match the LNA input impedance and maximize radiation diagram. Both are co-integrated directly on the silicon chip. The circuit is dedicated to automotive radar applications at 80GHz. The measurement results of the co-integrated LNA exhibit a gain and NF of 26dB and 5dB respectively with a power consumption of 20mW, while the antenna shows a simulated gain of 0dB.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114470018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A mmW low power VCO with high tuning range in 28nm FDSOI CMOS technology 基于28nm FDSOI CMOS技术的mmW低功率压控振荡器
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050037
M. Vallet, O. Richard, Y. Deval, D. Belot
{"title":"A mmW low power VCO with high tuning range in 28nm FDSOI CMOS technology","authors":"M. Vallet, O. Richard, Y. Deval, D. Belot","doi":"10.1109/ICECS.2014.7050037","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050037","url":null,"abstract":"A 28nm FDSOI CMOS low power VCO working at 40 GHz frequency is presented in this paper. The VCO core only consumes 6mW from a 1 V supply voltage. A wide tuning range of 18.5 % from 38.3 GHz to 46.1 GHz is reached with a tuning voltage from 0 to 1 V. A phase noise higher than -120.5 dBc/Hz at 10 MHz offset has been observed after post-layout simulations. A variable inductance approach has been chosen in order to maintain a sufficiently low phase noise despite significant constraints caused by the advanced technology nodes and the large tuning range needed.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124031377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Small area charge pump using low voltage capacitors 使用低压电容器的小面积电荷泵
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050103
N. Dumas, V. Frick, Jerome Heitz, C. Lallement, L. Hébrard
{"title":"Small area charge pump using low voltage capacitors","authors":"N. Dumas, V. Frick, Jerome Heitz, C. Lallement, L. Hébrard","doi":"10.1109/ICECS.2014.7050103","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050103","url":null,"abstract":"There are two main families of charge pumps: parallel and stacking. In this paper, we propose to compare a design that is a combination of both with the more common parallel structure. Its main advantage is to make use of only low voltage capacitors as, for a stacking architecture but without its drawback. The hereafter detailed model shows that with the same capacitors the proposed structure would be less efficient. However this handicap is counterbalanced by the fact that low voltage capacitors have a better sheet capacitance. It is demonstrated that the silicon area of the proposed structure is smaller, up to three stages included, compared to a parallel type of charge pump with ideal switches.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Numerical analysis of nano schottky junctions for developing novel sub-20 nm electronic devices 用于开发新型亚20nm电子器件的纳米肖特基结数值分析
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050032
K. Eledlebi, M. Ismail, M. Rezeq
{"title":"Numerical analysis of nano schottky junctions for developing novel sub-20 nm electronic devices","authors":"K. Eledlebi, M. Ismail, M. Rezeq","doi":"10.1109/ICECS.2014.7050032","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050032","url":null,"abstract":"Nano metal-semiconductor contacts in sub-20 nm range have showed unusual electrical characteristics compared to conventional diodes. New devices based on nano Schottky junction have been proposed to overcome the limitations of CMOS devices. Here we introduce a new theoretical approach for studying the enhancement of the electric field at the interface, and then the net current along the junction. The results revealed a dominant tunneling current at the reverse bias for low n-dope semiconductor substrates. Whereas for high n-dope substrates, the thermionic current is dominant at the forward bias. We have used a finite element simulation software (COMSOL) to analyze the electrical characteristics of nano Schottky diodes, and compare the theoretical results with experimental data.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127545362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A proof-of-concept superregenerative QPSK transceiver 概念验证超再生QPSK收发器
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049948
Alexis Lopez-Riera, Pere Palà-Schönwälder, J. Bonet-Dalmau, F. X. Moncunill-Geniz, Francisco del Águìla López, M. R. Giralt-Mas
{"title":"A proof-of-concept superregenerative QPSK transceiver","authors":"Alexis Lopez-Riera, Pere Palà-Schönwälder, J. Bonet-Dalmau, F. X. Moncunill-Geniz, Francisco del Águìla López, M. R. Giralt-Mas","doi":"10.1109/ICECS.2014.7049948","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049948","url":null,"abstract":"In this paper we present a description and experimental verification of an HF-band proof-of-concept superregenerative transceiver for QPSK signals. We describe a simple implementation of an all-digital, FPGA-based, QPSK transmitter section. On the receiver side, the quench signal is generated in the same FPGA with a minimum of analog circuitry. As the main novelty, we present a simple synchronization scheme suitable for packetized transmissions.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130004578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A technique for the identification of trapping sets in LDPC codes LDPC码中捕获集的识别技术
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050116
Christos Vasilopoulos, Vassilis Paliouras
{"title":"A technique for the identification of trapping sets in LDPC codes","authors":"Christos Vasilopoulos, Vassilis Paliouras","doi":"10.1109/ICECS.2014.7050116","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050116","url":null,"abstract":"In this paper we consider the problem of identifying trapping sets in Low Density Parity Check codes (LDPC), which is a hard NP-complete problem, as conjectured in [1]. We introduce a method for identifying trapping sets in LDPC codes. The proposed method is flexible and parametric. Furthermore it achieves low complexity and execution time and low memory requirements.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132173919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient micro-bump assignment for RDL routing in 3DICs 3dic中RDL路由的高效微碰撞分配
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049955
Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen
{"title":"Efficient micro-bump assignment for RDL routing in 3DICs","authors":"Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen","doi":"10.1109/ICECS.2014.7049955","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049955","url":null,"abstract":"For the signal connections between two adjacent dies in 3D ICs, the RDL routing from IO pads to micro-bumps plays an important role In this paper, given a set of micro-bumps and a set of connecting nets on the upper and lower RDLs between two adjacent dies, based on the testing of single-layer routing[7], an efficient algorithm including initial matching-based micro-bump assignment and rip-up-and-reroute-based reassignment is proposed to assign all the given nets on the micro-bumps for RDL routing. Compared with Kuan's algorithmic for micro-bump assignment in using Yan's single-layer routing algorithm [7] for RDL routing, the experimental results show that our proposed approach obtains shorter wirelength and reduces 73.7% of the CPU time to assign all the nets onto micro-bumps and guarantee 100% routability of single-layer RDL routing for five tested examples.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A low noise op-amp transimpedance amplifier for LIDAR applications 一种用于激光雷达的低噪声运放通阻放大器
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050054
A. Auckloo, R. C. Tozer, J. David, C. Tan
{"title":"A low noise op-amp transimpedance amplifier for LIDAR applications","authors":"A. Auckloo, R. C. Tozer, J. David, C. Tan","doi":"10.1109/ICECS.2014.7050054","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050054","url":null,"abstract":"This paper reports design methodology, implementation and characterisation of a low noise op-amp transimpedance amplifier. An equivalent input noise current of 3 pA/√Hz is reported, making it suitable for low noise applications such as LIDAR.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125430054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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