Mickael Lanoe, Matteo Bordin, Dominique Heller, P. Coussy, C. Chavet
{"title":"A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code","authors":"Mickael Lanoe, Matteo Bordin, Dominique Heller, P. Coussy, C. Chavet","doi":"10.1109/ICECS.2014.7050092","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050092","url":null,"abstract":"The P project gathers industrial and academic partners to address the issue of a modeling approach and automatic code generation for critical embedded systems. Works target the definition of an open design flow which integrates qualified tools to produce both hardware and software implementations. This paper introduces the project through two code generators that allow generating Ada, C and VHDL from Simulink. Application of the design flow to two industrial case studies is finally presented.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126149023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sizing of the physical layer of a RF intra-chip communications","authors":"M. Hamieh, M. Ariaudo, S. Quintanel, Y. Louët","doi":"10.1109/ICECS.2014.7049947","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049947","url":null,"abstract":"In this paper we size a RF intra-chip communications based on Orthogonal Frequency Division Multiple Access (OFDMA) modulation which allows data rate and message recipient reconfiguration. Firstly, we present the advantages of this modulation such as providing flexible and high-speed data transmission. Then, we study the impact of the RF-interconnect channel shape on the transmission in terms of required transmission power. Finally, we present the effect of the channel composed of the line and its multiple access on the transfer of information and we perform a channel equalization to overcome this undesired effect.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131600968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Chougrani, J. Schwoerer, Pierre-Henri Horrein, A. Baghdadi, F. Dehmas
{"title":"UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN","authors":"H. Chougrani, J. Schwoerer, Pierre-Henri Horrein, A. Baghdadi, F. Dehmas","doi":"10.1109/ICECS.2014.7050123","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050123","url":null,"abstract":"Ultra-wideband impulse radio (UWB-IR) has demonstrated strong advantages in the short range sensor networks in terms of low power, data rate scalability and low complexity implementation. This is why it was included in recently adopted IEEE 802.15.6 standard for wireless body area networks (BAN) as physical layer. In this paper, a hybrid architecture combining coherent and non-coherent receivers is proposed. Specific digital algorithms taking advantages of each radio front-end have been developed for 802.15.6 UWB-IR. Simulation reveals that the proposed architecture can achieve a packet error rate less than 10% for all IEEE 802.15.6 standard channel models and bit error rate less then 10-4 when considering the uniformity of bits errors.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Towards multiphysics simulations of integrated circuits","authors":"M. Garci, J. Kammerer, L. Hébrard","doi":"10.1109/ICECS.2014.7050114","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050114","url":null,"abstract":"Although the electrical benefits are greatly increasing in miniaturized integrated circuits, their corresponding design and reliability issues are also being raised. This work aims at the multiphysics simulation of integrated circuits that allows the designer to monitor the electrical, thermal and mechanical long term behaviour of the circuit from its early design stages. The multi-physics simulation tool is based on the direct method where three networks, i.e. an electrical, a thermal and a mechanical network, are directly linked and simulated with a unique circuit simulator. The tool was developed in a standard CAD environment, i.e. Cadence®. The way the three networks are built is described. In addition, to achieve multiphysics simulations, conventional CMOS models have to be replaced by specific multiphysics models that take additional physical effects into account, such as thermal effects, hot carriers induced ageing and their impact on the device performances. The modelling approaches as well as some simulation results are provided. Finally, the paper discusses the remaining prospective work to be able to perform electro-thermo-mechanical simulations of complex integrated systems.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127340766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digital hardware optimization for 1.5-GHz high-speed DDFS","authors":"Keerthi S. Asok, Karuna P. Sahoo","doi":"10.1109/ICECS.2014.7050093","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050093","url":null,"abstract":"This paper describes the design optimization and analysis of the digital hardware of a high-speed direct digital frequency synthesizer (DDFS) implemented using the NanGate 45nm Open Cell library. The digital blocks of the DDFS generate 13-bit accurate sinusoidal waveform in the frequency range of 0-500 MHz. The DDFS uses a 1.5 GHz input clock, a ROM-less phase to amplitude converter (PAC) based on the CORDIC algorithm, and has a frequency tuning resolution of 1 mHz. Fixed-point simulations and analysis were performed to obtain the finite hardware bit-widths to meet the desired Signal-to-Noise-Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) performance. Multiple quantization schemes were compared and the optimum scheme, which meets the hardware timing constraints and the desired system performance, is selected for the final hardware implementation.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125174704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Dianat, A. Attaran, R. Rashidzadeh, R. Muscedere
{"title":"Resonant-based test method for MEMS devices","authors":"A. Dianat, A. Attaran, R. Rashidzadeh, R. Muscedere","doi":"10.1109/ICECS.2014.7050012","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050012","url":null,"abstract":"In this paper a test method for capacitive Micro-Electro-Mechanical Systems (MEMS) is presented. The proposed method utilizes the principle of resonant circuits to detect structural defects of capacitive MEMS devices. It is shown that a small variation of MEMS capacitance due to a defect alters the resonance frequency considerably. It is also shown that the variation of the output amplitude can be observed for fault detection if an inductor with a high quality factor is employed in the test circuit. Simulation results using an implemented MEMS comb-drive indicate that the proposed method can detect common faults such as missing, broken and short fingers.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125580020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Konstantinos Gyftakis, Iraklis Anagnostopoulos, D. Soudris, D. Reisis
{"title":"A MapReduce framework implementation for Network-on-Chip platforms","authors":"Konstantinos Gyftakis, Iraklis Anagnostopoulos, D. Soudris, D. Reisis","doi":"10.1109/ICECS.2014.7049936","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049936","url":null,"abstract":"All facets of society are generating increasing amounts of data confirming the term big data for modern applications. The next generation of embedded systems will be dominated by such smart applications offering a wide range of communication services. Driven also by hardware changes and the adoption of the many-core architectural template, a better resource management scheme is required. MapReduce is a programming model capable of processing large data sets with a parallel distributed algorithm using a large number of processing nodes. In this paper, we present a MapReduce framework for an embedded many-core Network-on-Chip platform with distributed shared memory characteristics. The proposed framework, which supports bare-metal systems, provides a scalable solution for data processing in a many-core system, while fully utilizing the platform's characteristics and achieving application speedup.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114387271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 130 nm CMOS IR-UWB receiver based on baseband cross-phase detection","authors":"M. Crepaldi, P. Ros, D. Demarchi","doi":"10.1109/ICECS.2014.7050110","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050110","url":null,"abstract":"This paper presents an IR-UWB receiver robustly detecting pulses w.r.t. in-band and out-of-band non-pulsed narrowband signals. The system cross-filters the baseband pulse detector output with two different transfer functions to detect fast UWB signals phase advance. The baseband output is indeed low-pass filtered and dynamically subtracted with incoming UWB pulses which have larger bandwidth occupation, hence a larger envelope derivative. The circuit is implemented in a 130 nm RFC-MOS technology and occupies an area of 1110×550μm2. Here we introduce the design of the receiver and show first early qualitative results showing reliable transmission of pulse events with a range in excess of 5 m and an integrated all-digital IR-UWB transmitter.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117023279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Capacitive kinetic energy harvesting: System-level engineering challenges","authors":"D. Galayko, A. Dudka, P. Basset","doi":"10.1109/ICECS.2014.7050127","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050127","url":null,"abstract":"This review paper presents a short overview of the energy harvesting technologies at microscale, and focus on challenges related to vibration energy harveters (VEHs) which use electrostatic (capacitive) transducers. These devices are the best candidates for microscale integration, since the electrostatic transducers are natively implemented in silicon microtechnologies (MEMS). The main challenges associated with electrostatic VEHs are related to the passive nature of the capacitive transducer. The latter can be seen as a variable capacitor, needed to be dynamically biased/pre-charged in order to convert vibrations into electricity. For this, a complex management of the charging/discharging electrical flow on the transducer is required: this is achieved with a conditioning circuit, studied in numerous works. Electrostatic kinetic energy harvester a multidomain complex system, containing several blocks, whose optimal design still a subject of advanced research. This paper reviews the challenges related to design of capacitive vibration energy harvesters at the system level, explains fundamental limitation of the capacitive vibration energy harvesters at micro scale, and overview the existing system-level solutions of capacitive VEHs.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129291194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit","authors":"Chen-Bo Hsu, Y. Hong, J. Kuo","doi":"10.1109/ICECS.2014.7049921","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049921","url":null,"abstract":"This paper presents a low-power optimization technique (LPOT) for a 1V pipelined RISC microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPOT, a 32-bit pipelined RISC microprocessor test circuit having 144,000 transistors with 3 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells. According to SPICE simulation results, during the 4-instruction GCD operation, the off-peak power consumption of this pipelined RISC CPU test circuit with the MTCMOS LPOT, designed using a 90nm CMOS technology, operating at 1V, has been reduced by 20% at the clock cycle of 1.35ns, as compared to the one using the conventional SVT one. The substantial saving on off-peak power consumption for the pipelined RISC CPU circuits via the MTCMOS LPOT could benefit for portable IT applications, where leakage power consumption is the key to battery life.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124635383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}