Digital hardware optimization for 1.5-GHz high-speed DDFS

Abstract

This paper describes the design optimization and analysis of the digital hardware of a high-speed direct digital frequency synthesizer (DDFS) implemented using the NanGate 45nm Open Cell library. The digital blocks of the DDFS generate 13-bit accurate sinusoidal waveform in the frequency range of 0-500 MHz. The DDFS uses a 1.5 GHz input clock, a ROM-less phase to amplitude converter (PAC) based on the CORDIC algorithm, and has a frequency tuning resolution of 1 mHz. Fixed-point simulations and analysis were performed to obtain the finite hardware bit-widths to meet the desired Signal-to-Noise-Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) performance. Multiple quantization schemes were compared and the optimum scheme, which meets the hardware timing constraints and the desired system performance, is selected for the final hardware implementation.