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Fault tolerant implementation of a SpaceWire interface SpaceWire接口的容错实现
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050060
Sebastian Taube, V. Petrovic, M. Krstic
{"title":"Fault tolerant implementation of a SpaceWire interface","authors":"Sebastian Taube, V. Petrovic, M. Krstic","doi":"10.1109/ICECS.2014.7050060","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050060","url":null,"abstract":"Due to cosmic radiation, semiconductor chips operating in space have to be protected particularly against Single Event Effects (SEE). The SpaceWire protocol is frequently used in space vehicles, connecting mission critical devices. To increase the reliability of a SpaceWire transceiver under these conditions, various fault tolerance concepts are presented, which protect the transceiver against Single Event Transients (SETs) and Upsets (SEUs). Within these concepts, the application of modular redundancy with information redundancy respectively with the error correction method at the SpaceWire protocol layer is combined to reduce the hardware overhead. This paper provides the evaluation of methods combining different circuit-level fault tolerant concepts with existing protocol-layer fault tolerance provided by SpaceWire standard. It will been shown that the concept utilizing Double Modular Redundancy is the most efficient one, while the application of hardware fault tolerance provides advantages only for high fault densities.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129196978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A digitally corrected ADC using a passive pulse frequency modulator 采用无源脉冲调制器的数字校正ADC
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050070
Eric Gutierrez, L. Hernández, Ulrich Gaier, S. Walter, Liang Zou
{"title":"A digitally corrected ADC using a passive pulse frequency modulator","authors":"Eric Gutierrez, L. Hernández, Ulrich Gaier, S. Walter, Liang Zou","doi":"10.1109/ICECS.2014.7050070","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050070","url":null,"abstract":"Pulse Frequency Modulators have been proposed recently as an alternative to ring oscillators in the implementation of Voltage-Controlled-Oscillators Analog to Digital Converters (VCO-ADC). In this paper, we propose a passive pulse frequency modulator in terms of the integration process that uses digital inverters only and provides a polyphase output similar to a ring oscillator. Oscillation depends on a passive RC circuit acting as oscillator time constant. The voltage-to-frequency characteristic of this oscillator shows a nonlinear relationship respect to the input voltage in a similar way as classical ring oscillators. However, in the proposed circuit the nonlinearity depends mainly in a predictable way from the RC product instead of supply voltage (Vdd), temperature or mismatch. We show in this paper how the nonlinearity can be corrected in the signal post-processing by a simple algorithm depending only on the RC time constant operating on the decimated data and circuit parameters that could be known.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127539388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effect of multi-scrolls distribution on image encryption 多卷轴分布对图像加密的影响
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050015
A. Radwan, S. Abd-El-Hafiz
{"title":"The effect of multi-scrolls distribution on image encryption","authors":"A. Radwan, S. Abd-El-Hafiz","doi":"10.1109/ICECS.2014.7050015","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050015","url":null,"abstract":"This paper introduces the mathematical formulation of a ID digital control multi-scroll chaotic jerk system. The eigenvalue analysis of such systems is presented and validated through different numerical examples. A generalized 2D multi-scrolls chaotic system is also presented with numerical examples. As an application, these ID and 2D chaotic systems are used in a simple encryption technique. Two different cases from each ID and 2D multi-scrolls, having a total of 12 scrolls under the same initial conditions, are utilized as a random source after postprocessing. Correlation coefficients, differential attack measures and histograms are used to evaluate the encrypted images as well as the effect of the used nonlinear block.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127722582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A simple structure AGC for synchronous capacitor resonant converter used in HIFU application 一种用于HIFU同步电容谐振变换器的结构简单的AGC
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050025
Xusheng Wang, Ming Zhang, X. Ren, F. Rodes, R. Denieport
{"title":"A simple structure AGC for synchronous capacitor resonant converter used in HIFU application","authors":"Xusheng Wang, Ming Zhang, X. Ren, F. Rodes, R. Denieport","doi":"10.1109/ICECS.2014.7050025","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050025","url":null,"abstract":"In this paper, an automatic gain control amplifier (AGC) is proposed. The proposed AGC aims at a large input and output swing with a rapid tracking capacity. Moreover, the proposed AGC has a quite simple structure, which is very important for High intensity focused ultrasound (HIFU) applications in which an array of identical circuits must be used. The designed circuit was simulated in a CMOS 0.35μm technology. The required performances have been confirmed by simulation results: a large ratio of input signal of 20 has been achieved; a good linearity with a relative error lower than 0.62% is observed; the output peak-to-peak signal can be as high as 2V; the tracking time is less than 6μs, for an input signal of 1MHz.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique 一种采用压缩乘法技术的超平行图像滤波数字像素传感器
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049997
Hongbo Zhu, K. Asada
{"title":"A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique","authors":"Hongbo Zhu, K. Asada","doi":"10.1109/ICECS.2014.7049997","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049997","url":null,"abstract":"A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invariant feature transform (SIFT) algorithm. A 108 × 96-pixel sensor was designed using a 0.18 μm CMOS process in a 5 mm×5 mm chip. By simulating the sensor at 100 MHz, the image filtering times for 5×5, 7×7, and 9×9 Gaussian kernels in the SIFT algorithm are 34 μs, 49 μs, and 83 μs, respectively. Such a high processing speed is very important for achieving the real-time performance when filtering high resolution images with large kernels.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimized implementation of memristor-based full adder by material implication logic 基于材料蕴涵逻辑的忆阻器全加法器的优化实现
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050047
Mehri Teimoory, A. Amirsoleimani, Jafar Shamsi, A. Ahmadi, S. Alirezaee, M. Ahmadi
{"title":"Optimized implementation of memristor-based full adder by material implication logic","authors":"Mehri Teimoory, A. Amirsoleimani, Jafar Shamsi, A. Ahmadi, S. Alirezaee, M. Ahmadi","doi":"10.1109/ICECS.2014.7050047","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050047","url":null,"abstract":"Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127857181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO 一个0.03mm2, 40nm CMOS 1.5GS/s全数字互补PWM-GRO
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049935
E. Prefasi, Eric Gutierrez, L. Hernández, S. Patón, S. Walter, Ulrich Gaier
{"title":"A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO","authors":"E. Prefasi, Eric Gutierrez, L. Hernández, S. Patón, S. Walter, Ulrich Gaier","doi":"10.1109/ICECS.2014.7049935","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049935","url":null,"abstract":"Nonlinearity is one of the main problems associated with VCO based noise shaping ADCs. Their open loop architecture does not permit correction of the nonlinear voltage to frequency response of the VCO by feedback. Recently, linearization of a VCO ADC by Pulse Width Modulation (PWM) pre-coding has been proposed. This work presents an area- and power-efficient realization of a new complementary PWM Gated Ring Oscillator (GRO) that can be used as input stage of an all-digital multi-stage ADC. Here, the analog input signal is encoded by two PWM modulators to drive two GRO's with a 2-level signal in a complementary way, thus eliminating the nonlinearity of the VCO's. In order to reduce power consumption the PWM modulator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. In order to show the efficiency of this new architecture a prototype has been fabricated and measured. The differential output of the PWM-GRO shows first order noise shaping and clocked at 1.5GHz consumes only 2.15mW from a single 1.1V supply. Integrating the output noise in a 20MHz bandwidth the equivalent FoM is 105fJ/conversion-step. The design occupies 0.03mm2 in a 40nm CMOS process.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"202 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120984906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Internal Vth cancellation scheme for RF to DC rectifiers used in RF energy harvesting 用于射频能量收集的射频到直流整流器的内部v消方案
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049965
S. Chouhan, K. Halonen
{"title":"Internal Vth cancellation scheme for RF to DC rectifiers used in RF energy harvesting","authors":"S. Chouhan, K. Halonen","doi":"10.1109/ICECS.2014.7049965","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049965","url":null,"abstract":"In this work, an internal threshold voltage (Vth) cancellation (IVC) scheme is proposed for the rectifiers used in the RF energy harvesting systems. Conventionally, the CMOS-based rectifier is used for performing RF to DC conversion. The proposed IVC scheme has been implemented in PMOST of the conventional CMOS rectifier. The single stage conventional and the proposed rectifiers have been designed and fabricated in a standard 0.18μm CMOS technology. The measurements have been done for the resistive load of 1 KΩ, 10 KΩ and 100 KΩ. In the measurement a 433 MHz RF signal with input power ranges from -24 to +10 dBm was used. The power conversion efficiency (PCE) is selected as a performance metric for the rectifiers. The conventional rectifier achieved maximum PCE of ≈16% at the RF input power of -8 dBm for the resistive load of 10 KΩ, while after implementing the proposed IVC scheme in the PMOST, the measured PCE was ≈35% at the same input power level.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117114733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Saliency oriented object image re-ranking 面向显著性的目标图像重排序
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7049999
Chao Xu, Yuan Gao, Miaojing Shi
{"title":"Saliency oriented object image re-ranking","authors":"Chao Xu, Yuan Gao, Miaojing Shi","doi":"10.1109/ICECS.2014.7049999","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7049999","url":null,"abstract":"For image retrieval, most users hope to retrieve a certain salient object instead of an obscure pattern in an image. This paper presents a novel object re-ranking algorithm based on visual saliency, which is employed to detect salient object regions in an image. The re-ranking is carried out with a SVM classifier on the salient regions to assure that the images ranked on the top of the list exhibit salient object pictures. To speed up the classifier training, a small code book (1K) is chosen. To improve the re-ranking efficacy, we employ the posterior probability of the salient region to adjust re-ranking, and derive an approximate formula of the posterior probability of the salient region. The formula is based on a hierarchical model, containing spatial information to compensate the feature disorder of the model of bags of visual words (BoVW). The posterior probability is calculated offline, so the online efficiency of re-ranking is high. Experiments demonstrate that our algorithm significantly improves online efficiency and saliency while possesses high accuracy of image retrieval.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116436770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OAPM: Fine-grained operand-aware power management with fast reaction time OAPM:具有快速反应时间的细粒度操作感知电源管理
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI: 10.1109/ICECS.2014.7050095
Salirti N. Farah, M. Bayoumi
{"title":"OAPM: Fine-grained operand-aware power management with fast reaction time","authors":"Salirti N. Farah, M. Bayoumi","doi":"10.1109/ICECS.2014.7050095","DOIUrl":"https://doi.org/10.1109/ICECS.2014.7050095","url":null,"abstract":"Power management is a crucial aspect of modern low power SoCs, but kernel-based approaches suffer from slow DVFS and power state adaptation. We propose OAPM, a power management scheme based on circuit-level operand activity that complements existing OS-based solutions with better system visibility. Operating at the cycle granularity, OAPM has very fast response time in requesting the appropriate power state via a two-stage algorithm. Simulations show potential savings of up to 70% when used with clock-gated Domino, depending on the activity profile.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124393444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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