A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO

Abstract

Nonlinearity is one of the main problems associated with VCO based noise shaping ADCs. Their open loop architecture does not permit correction of the nonlinear voltage to frequency response of the VCO by feedback. Recently, linearization of a VCO ADC by Pulse Width Modulation (PWM) pre-coding has been proposed. This work presents an area- and power-efficient realization of a new complementary PWM Gated Ring Oscillator (GRO) that can be used as input stage of an all-digital multi-stage ADC. Here, the analog input signal is encoded by two PWM modulators to drive two GRO's with a 2-level signal in a complementary way, thus eliminating the nonlinearity of the VCO's. In order to reduce power consumption the PWM modulator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. In order to show the efficiency of this new architecture a prototype has been fabricated and measured. The differential output of the PWM-GRO shows first order noise shaping and clocked at 1.5GHz consumes only 2.15mW from a single 1.1V supply. Integrating the output noise in a 20MHz bandwidth the equivalent FoM is 105fJ/conversion-step. The design occupies 0.03mm2 in a 40nm CMOS process.