基于材料蕴涵逻辑的忆阻器全加法器的优化实现

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2014-12-01 DOI:10.1109/ICECS.2014.7050047

Mehri Teimoory, A. Amirsoleimani, Jafar Shamsi, A. Ahmadi, S. Alirezaee, M. Ahmadi

{"title":"基于材料蕴涵逻辑的忆阻器全加法器的优化实现","authors":"Mehri Teimoory, A. Amirsoleimani, Jafar Shamsi, A. Ahmadi, S. Alirezaee, M. Ahmadi","doi":"10.1109/ICECS.2014.7050047","DOIUrl":null,"url":null,"abstract":"Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"55","resultStr":"{\"title\":\"Optimized implementation of memristor-based full adder by material implication logic\",\"authors\":\"Mehri Teimoory, A. Amirsoleimani, Jafar Shamsi, A. Ahmadi, S. Alirezaee, M. Ahmadi\",\"doi\":\"10.1109/ICECS.2014.7050047\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.\",\"PeriodicalId\":133747,\"journal\":{\"name\":\"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"55\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2014.7050047\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2014.7050047","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 55

摘要

近年来，基于忆阻器的应用和电路受到越来越多的关注。此外，忆阻器在逻辑电路设计中也有应用。物质蕴涵逻辑是记忆电阻器的主要研究领域之一。本文提出了一种基于材料蕴涵逻辑的忆阻器全加法器优化设计方法。与典型的基于cmos的8位全加法器相比，该设计需要27个忆阻器和更少的面积。该全加法器只需要184个计算步骤，使全加法器的设计速度提高了20%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimized implementation of memristor-based full adder by material implication logic

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.

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来源期刊

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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