IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"TT-RRAM: Joint Improvement of Sparsity and Repetition in Tensor-Train Inference With Fused Processing on RRAM Accelerators","authors":"Fang-Yi Gu;Pin-Hong Liu;Ing-Chao Lin;Bo Yuan","doi":"10.1109/TCAD.2025.3604731","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3604731","url":null,"abstract":"Deep neural networks compressed using tensor-train decomposition, known as TT-DNNs, significantly reduce model size to decrease storage requirements but suffer from more frequent data movement during inference. To address this issue, resistive random access memory (RRAM)-based deep neural network (DNN) accelerators, by leveraging computing-in-memory, can mitigate the data movement and efficiently execute the vector–matrix multiplication (VMM) operations required during inference, making them an ideal candidate for accelerating the inference for TT-DNNs. However, RRAM-based accelerators face three challenges in TT-format DNN inference: 1) weights distribution on the RRAM crossbar with low sparsity and repetition; 2) low input sparsity; and 3) high data dependencies and storage overhead during inference. To address these challenges, we propose three corresponding methods: 1) base-offset splitting (BOS) to improve the weights distribution on the crossbar, thereby enhancing performance potential; 2) inverse-input reusing (IIR) to enhance the sparsity of inputs during inference; and 3) fused scheduling (FS) to reorganize the computation order and leveraging the parallel processing capabilities of the RRAM-based accelerator to improve overall inference efficiency while also reducing data dependencies and storage overhead. Experimental results demonstrate that our proposed methods achieve a <inline-formula> <tex-math>$3.44times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$5.53times $ </tex-math></inline-formula> performance improvement and 55.6%–67.1% energy savings compared with the state-of-the-art RRAM-based accelerator, while also reducing storage overhead by 66.7%–99.1%.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1649-1662"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EvaCAM: A Circuit-Level Evaluation Tool for General Content Addressable Memories","authors":"Liu Liu;Mohammad Mehdi Sharifi;Kunshi Wang;Ruibin Mao;Kai Ni;Can Li;Xunzhao Yin;Michael Niemier;Xiaobo Sharon Hu","doi":"10.1109/TCAD.2025.3605857","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3605857","url":null,"abstract":"Content addressable memories (CAMs) are special-purpose in-memory computing (IMC) units that support parallel searches directly in memory. There is growing interest in CAMs for data-intensive applications such as machine learning, data mining, and bioinformatics, which has led to a rapidly growing CAM design space. CAM cells can be implemented exclusively by CMOS or with various nonvolatile memory (NVM) devices. In addition to traditional binary and ternary CAMs (BCAMs and TCAMs), analog CAM (ACAM) and multibit CAM (MCAM) designs have recently been introduced, which could further improve density and also support unique in-memory distance functions. Furthermore, aside from the widely used exact match function, CAM-based approximate match functions, such as threshold match and best match, have been proposed to further extend the utility of CAMs to new application spaces. As the CAM design space is large, evaluating different CAM design options for a given application is both crucial and challenging. This article presents EvaCAM, a circuit-level modeling and evaluation tool for CAMs. EvaCAM supports TCAM, ACAM, and MCAM designs implemented in either CMOS or NVMs, for both exact and approximate match functions. It also allows for the exploration of different CAM designs under various optimization targets. EvaCAM has been validated against measured data from fabricated chips and detailed SPICE simulations. A comprehensive design space exploration for CAMs is provided to illustrate the impact of various design decisions and to demonstrate the use cases of EvaCAM.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1663-1676"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Reliable ESD 3D-Integrated Design and Simulation (3D-IDS) Methodology for Wafer-on-Wafer Stacked DRAM","authors":"Xuerong Jia;Song Wang;Yixin Guo;Fujun Bai;Bing Yu;Xiyuan Feng;Yi Liu;Zhiwei Liu;Li Geng","doi":"10.1109/TCAD.2025.3607152","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607152","url":null,"abstract":"The electrostatic discharge (ESD) protection design and verification methodology are particularly important for the wafer-on-wafer (WoW) stacked system due to the miniaturization of vertical interconnect cells, the simplification of vertical drivers, and the complexity of the 3D power network. This article introduces an ESD 3D-integrated design and simulation (3D-IDS) methodology for WoW 3D stacked DRAM, which incorporates customized ESD protection devices and vertical interconnect models, creating a comprehensive 3D ESD discharging network, addressing the challenges posed by high-density vertical connections in WoW 3D stacks. This 3D ESD network encompasses all crucial elements of 3D ESD discharging paths, including on-chip ESD protection devices and a comprehensive 3D power/ground discharge network. Silicon measurement results confirm that the ESD human body model (HBM) and charged device model (CDM) limitations corroborate the simulation forecasts. This validation confirms that the proposed ESD 3D-IDS methodology is a reliable and effective approach for ESD protection design and optimization in WoW stacked DRAM.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1625-1634"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CirOPT: Toward Effective Combinational Equivalence Checking via Compiler Optimization","authors":"Shaoke Cui;Chuan Luo;Zhenwei Yang;Jiabao Lin;Wei Wu;Chanjuan Liu;Shaowei Cai;Chunming Hu","doi":"10.1109/TCAD.2025.3608060","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3608060","url":null,"abstract":"Combinational equivalence checking (CEC) is essential for verifying the correctness of circuit designs. With the growing complexity of circuits, effective verification techniques have become increasingly critical. Recently, a conjunctive normal form (CNF)-based approach, converting circuits to CNF for Boolean satisfiability (SAT) solvers, has shown competitive performance compared to state-of-the-art hybrid SAT sweeping approaches. The capability of this CNF-based approach depends on effective CNF conversion. This work presents CirOPT, which is the first CNF conversion method using compiler optimization to equivalently simplify circuits. Extensive experiments are conducted on a broad range of real-world benchmarks, which are far more than the number of benchmarks typically used in empirical studies. The results reveal that, when paired with the state-of-the-art CNF SAT solver Kissat, CirOPT considerably outperforms existing approaches in CEC.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1841-1851"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2026.3671389","DOIUrl":"https://doi.org/10.1109/TCAD.2026.3671389","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"C2-C2"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11450542","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"QuickCell: Fast Automatic Design of Standard Cells for Silicon Dangling Bond Logic","authors":"Jan Drewniok;Marcel Walter;Samuel Sze Hang Ng;Konrad Walus;Robert Wille","doi":"10.1109/TCAD.2025.3605537","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3605537","url":null,"abstract":"In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology due to its integration density and operating frequency. This advancement is driving the development of comprehensive design automation workflows, including physical simulators and gate design tools. Unlike conventional circuit technology, where logic is implemented through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, standard logic functions like <sc>or</small>, <sc>and</small>, <sc>nand</small>, and so on can be implemented, which are usually provided as standard cells in design processes. However, finding such arrangements that implement a given Boolean function is a tremendously complex task that involves considering numerous candidates and verifying them through computationally expensive physical simulation. Hence, the automatic obtainment of SiDB logic layouts is thus far limited to simple two-input functions only, which already require substantial computation resources. In contrast, conventional physical design algorithms for VLSI have long transitioned from single-gate considerations to multiinput standard cells. To address this challenge, this article proposes QuickCell, a fast algorithm for automatic standard cell design for SiDB logic that uses dedicated search space pruning techniques. In an extensive experimental evaluation, it is demonstrated that combining these pruning techniques yields: 1) a drastic reduction of the search space amounting to up to six orders of magnitude; 2) a corresponding decrease of the runtime by up to a factor of 91; 3) the capability to handle more complex functionality, as, for example, utilized in standard cells, for the first time, significantly narrowing the gap between SiDB logic and conventional CMOS design paradigms; and 4) a significant speedup compared to physical simulation (up to a factor of 10000), with near independence from the number of input–output (I/O) pins when determining the nonoperationality of a given layout. This efficiency makes these techniques—and by extension QuickCell—a powerful enabler for the design of complex standard cells.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1769-1781"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11146893","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs","authors":"Oussama Oulkaid;Bruno Ferres;Matthieu Moy;Pascal Raymond;Mehdi Khosravian Ghadikolaei","doi":"10.1109/TCAD.2025.3608647","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3608647","url":null,"abstract":"The behavior of any electronic system can be traced back to how its constituting components physically interact with each other. Such low-level interactions explain how specific states of a given circuit are physically possible. Some circuit states can be erroneous, e.g., applying a voltage stress greater than what some device can tolerate. It is of particular importance to know whether such errors can happen on a given circuit, so that required corrections can be made. Identifying errors requires some circuit modeling technique and a way to explore the state space of the circuit model (which may be very large if at all finite). In this work, we show the limitations of classical verification techniques and propose a new approach based on formal methods to overcome them. We propose new circuit semantics for transistor-level descriptions from 1) recalling and improving existing semantics and 2) introducing novel alternate ones. We then demonstrate their usage in our verification framework—which makes use of a satisfiability modulo theories (SMT) solver—to verify specific electric properties of circuits. Specifically, we address the problem of the search for circuit transistors that are subject to electrical overstress (EOS). We draw interesting conclusions by comparing the presented circuit semantics, both formally and via experimental benchmarks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1852-1866"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SALSy: Security-Aware Layout Synthesis","authors":"Mohammad Eslami;Tiago D. Perez;Samuel Pagliarini","doi":"10.1109/TCAD.2025.3607131","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607131","url":null,"abstract":"Integrated circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of hardware Trojans (HTs), can give an adversary access to privileged data and/or the means to corrupt the IC’s internal computation. Postfabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account, and at the same time, this article proposes a methodology for security-aware layout synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power–performance–area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the tradeoffs between PPA and security are considered, and a chip is fabricated in a 65-nm CMOS commercial technology for validation purposes—a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power to achieve significantly improved security metrics.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1704-1717"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TranSIC: A Storage in Computing Framework for Designing Efficient Transformer Accelerators in Energy-Constrained Scenarios","authors":"Ming Han;Jin Wu;Jian Dong;Ye Wang;Heng Liu;Gang Qu","doi":"10.1109/TCAD.2025.3608002","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3608002","url":null,"abstract":"Intelligent applications such as wearable health monitors, IoT devices, nano-drones, and embodied intelligence systems are increasingly deployed in energy-constrained environments. Though Transformer models offer advanced processing capabilities, their integration is limited by energy and computational constraints. Extensive research has shown that data movement, particularly for large Transformer weights, is the primary source of energy consumption, accounting for up to 37% of total energy use. Recent techniques like processing in-memory (PIM) and processing near-memory (PNM) are hard to fundamentally reduce the number of data movements, limiting their effectiveness in lowering energy consumption. This article investigates storage in computing (SIC), integrating weight matrices directly into computation circuits, thereby eliminating external memory access during inference and reducing operand data movement significantly. To realize SIC, we propose TranSIC, an innovative approach to create efficient Transformer accelerators with minimized data movement. Key advancements facilitating practical SIC implementation include a reuse strategy to reduce required SIC units and a low-overhead optimization method for this strategy to decrease data routing overhead. Experimental results demonstrate that TranSIC achieves up to <inline-formula> <tex-math>$8.65times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$56.24times $ </tex-math></inline-formula> energy efficiency over state-of-the-art PIM and traditional approaches, respectively.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1718-1731"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Joint Data Transmission Scheme With Improved CAC for 3D-SICs Based on Multiple TSV Subarrays","authors":"Huan Yang;Xiaole Cui;Chen Wei;Juncheng Pu;Zhaohong Lin;Xing Zhang","doi":"10.1109/TCAD.2025.3607139","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607139","url":null,"abstract":"Through-silicon via (TSV) is one of the key components enabling vertical electrical interconnects in 3-D stacked integrated circuits (3D-SICs). The high density of TSVs poses substantial crosstalk challenges due to the coupling effects. Traditional crosstalk avoidance codes (CACs) mitigate the crosstalk but bring substantial codec area. The crosstalk suppression capability of CACs is also degraded by the edge effects of TSV array. Although the existing bus partition methods alleviate the drastic codec area increase of CACs, they result in higher bit overhead because the data to be transmitted by each subarray is encoded independently. This work proposes the joint data transmission (JDT) scheme, in which the data to be transmitted by multiple TSV subarrays are encoded jointly. It is proven that the bit overhead of the JDT scheme is less than that of the independent data transmission (IDT) scheme. A systematic design method is proposed to optimize the subarray parameters to minimize the total area of the codecs and TSVs. Furthermore, a new CAC technique named exhaustive reduced adjacent transition CAC (ERAT-CAC) is proposed to improve the crosstalk suppression capability under the edge effects by constraining adjacent signal transitions. The simulation results show that the proposed JDT scheme with the ERAT-CAC has better crosstalk suppression capability under the edge effect compared with fibonacci numeral system (FNS)-forbidden pattern free (FPF)-CAC, FNS-forbidden transition free (FTF)-CAC, and 3D-DPS-CAC, along with smaller area overhead and lower transmission power.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1611-1624"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}