IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"MinMaxEntropy: Bound Model Errors for Side-Channel Leakages From Information Theory","authors":"Changhai Ou;Zhenfang Qiu;Xingshuo Han;Fan Zhang;Shihui Zheng;Fei Yan","doi":"10.1109/TCAD.2025.3541187","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541187","url":null,"abstract":"Side-channel attacks and evaluations have been incessantly pursuing an accurate leakage model and try to address the following question: “How good is my leakage model?” However, the existing works do not well alleviate the attackers and evaluators from model assumption error and estimation error. The recent work named maximum entropy distribution (MED) model does not depend on any assumptions but uses nonlinear programming Newton-Raphson method to fit the leakage distribution, thus avoiding assumption error and making the estimation error arbitrarily small. It tries to address a more fundamental problem: “How to achieve the optimal leakage model?,” but still have to face with two issues: 1) the large deviation of MED model from leakage distribution and 2) the difficulty in determining the moments required in model profiling. In this article, we first introduce the nonlinear programming optimizations Levenberg-Marquardt and Conjugate Gradient methods to tackle the first issue. We then exploit Hopfield neural network to solve the minimum entropy for leakage model. Unlike the MED indicating the theoretically most unbiased, objective and reasonable leakage model, the minimum entropy corresponds to the theoretically most biased, subjective and unreasonable leakage model. This facilitates us to build a MinMaxEntropy bound from the maximum entropy and minimum entropy for estimation errors in leakage model, which theoretically represents the amount of information contained on unused higher moments. This bound well provides theoretical support for the moments constraints required to profile the MED model, thus well tackling the second issue. Experimental results fully demonstrate the superiority of our above schemes.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3247-3259"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir","authors":"Sosei Ikeda;Hiromitsu Awano;Takashi Sato","doi":"10.1109/TCAD.2025.3541565","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541565","url":null,"abstract":"A delayed feedback reservoir (DFR) is a hardware-friendly reservoir computing system. Implementing DFRs in embedded hardware requires efficient online training. However, two main challenges prevent this: 1) hyperparameter selection, which is typically done by offline grid search, and 2) training of the output linear layer, which is memory-intensive. This article introduces a fast and accurate parameter optimization method for the reservoir layer utilizing backpropagation and gradient descent by adopting a modular DFR model. A truncated backpropagation strategy is proposed to reduce memory consumption associated with the expansion of the recursive structure while maintaining accuracy. The computation time is significantly reduced compared to grid search. In addition, an in-place Ridge regression for the output layer via 1-D Cholesky decomposition is presented, reducing memory usage to be 1/4. These methods enable the realization of an online edge training and inference system of DFR on an FPGA, reducing computation time by about 1/13 and power consumption by about 1/27 compared to software implementation on the same board.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3323-3335"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MTrain: Enable Efficient CNN Training on Heterogeneous FPGA-Based Edge Servers","authors":"Yue Tang;Alex K. Jones;Jinjun Xiong;Peipei Zhou;Jingtong Hu","doi":"10.1109/TCAD.2025.3541486","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541486","url":null,"abstract":"FPGA-based edge servers are used in many applications in smart cities, hospitals, retail, etc. Equipped with heterogeneous FPGA-based accelerator cards, the servers can be implemented with multiple tasks, including efficient video prepossessing, machine learning algorithm acceleration, etc. These servers are required to implement inference during the daytime while retraining the model during the night to adapt to new environments, domains, or new users. During the retraining, conventionally, the incoming data are transmitted to the cloud, and then the updated machine learning models will be transferred back to the edge server. Such a process is inefficient and cannot protect users’ privacy, so it is desirable for the models to be directly trained on the edge servers. Deploying convolutional neural network (CNN) training on heterogeneous resource-constrained FPGAs is challenging since it needs to consider both the complex data dependency of the training process and the communication bottleneck among different FPGAs. Previous multiaccelerator training algorithms select optimal scheduling strategies for data parallelism (DP), tensor parallelism (TP), and pipeline parallelism (PP). However, PP cannot deal with batch normalization (BN) which is an essential CNN operator, while purely applying DP and TP suffers from resource under-utilization and intensive communication costs. In this work, we propose MTrain, a novel multiaccelerator training scheduling strategy that transfers the training process into a multibranch workflow, thus independent suboperations of different branches are executed on different training accelerators in parallelism for better utilization and reduced communication overhead. Experimental results show that we can achieve efficient CNN training on heterogeneous FPGA-based edge servers with <inline-formula> <tex-math>$1.07times $ </tex-math></inline-formula> –<inline-formula> <tex-math>$2.21times $ </tex-math></inline-formula> speedup under 15-GB/s peer-to-peer bandwidth compared to the state-of-the-art work.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3395-3408"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Asymmetric and Adaptive Error Correction in STT-MRAM","authors":"Surendra Hemaram;Mehdi B. Tahoori;Francky Catthoor;Siddharth Rao;Sebastien Couet;Tommaso Marinelli;Valerio Pica;Gouri Sankar Kar","doi":"10.1109/TCAD.2025.3541188","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541188","url":null,"abstract":"Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising alternative to conventional CMOS memory technologies for on-chip cache replacement. Due to its superior access speeds, high endurance, and scalability, it is being extensively considered a promising candidate for last-level cache replacement. This technology has reached considerable industrial maturity, with several foundries now offering this emerging technology. Despite its advantages, STT-MRAM faces reliability challenges, primarily due to its asymmetric error characteristics during write and read operations, where the likelihood of a bit transitioning from <inline-formula> <tex-math>$1rightarrow 0$ </tex-math></inline-formula> differs from that of <inline-formula> <tex-math>$0rightarrow 1$ </tex-math></inline-formula>. Conventional Error Correcting Codes (ECCs) do not account for such asymmetry between these bit-flip types and fall short of providing balanced error correction. This article introduces an efficient asymmetric and adaptive error correction in STT-MRAM based on the Hamming weight of data bits that operates with negligible overhead alongside a standard ECC framework. Our simulation findings indicate that the proposed technique offers substantial enhancement in reliability, measured by a cache word/block error rate, tested across the last level cache data for various SPEC CPU2017 benchmarks. This enhancement in reliability is achieved without inserting excessive memory and hardware overhead, and without impacting system performance, presenting a compelling case for enhancing the operational reliability of STT-MRAM.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3336-3349"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hierarchical Formal Verification of Hardware","authors":"Huaixi Lu;Yue Xing;Aarti Gupta;Sharad Malik","doi":"10.1109/TCAD.2025.3541567","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541567","url":null,"abstract":"Scaling hardware formal verification (FV) has been an ongoing challenge due to the state space explosion problem. In this article, we introduce a bottom-up verification methodology that leverages design hierarchy by using sound abstractions at each level in the hierarchy to decompose the overall FV problem into a set of smaller, more manageable FV tasks.We use the recently proposed instruction-level abstraction (ILA) as a complete specification at each level of the design hierarchy. We then utilize ILA-based verification methods to check correctness of modules composed at that level. The ILA specification includes an interface specification for each module and interface checks for verifying correct intermodule communication. This approach enables compositional verification with the following guarantee: if each hardware component refines its ILA specification and passes the interface checks, then the register-transfer level composition refines the ILA composition. We then show how this compositional verification methodology facilitates a bottom-up hierarchical verification approach, where the specification at one level serves as the implementation at the next higher level. We demonstrate the increased scalability of our methodology through several case studies, including complex modules in two deep learning accelerators (FlexASR and NVDLA), where verification fails to complete on the flat designs.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3629-3642"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MULSAM: Multidimensional Attention With Hardware Acceleration for Efficient Intrusion Detection on Vehicular CAN Bus","authors":"He Xu;Xiaokang Shi;Hansheng Liu;Yanwen Wang;Jiwu Lu;Haibo Zeng;Renfa Li;Di Wu","doi":"10.1109/TCAD.2025.3541566","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541566","url":null,"abstract":"Controller area network (CAN) protocol is an efficient standard enabling communication among electronic control units (ECUs). However, the CAN bus is vulnerable to malicious attacks because of a lack of defense features. In this article, a novel vehicle intrusion detection system (IDS) is developed. The challenge is that existing techniques of IDSs rarely consider attacks with small-batch, which are characterized by their small attack scale and concealed attack patterns, posing a significant threat to driving safety. To solve this problem, we developed an algorithm model that merges multidimensional long short-term memory (MD-LSTM) and self-attention mechanism (SAM), shortly named MULSAM. The MULSAM model was compared with other baseline models, including stacked long short-term memory (LSTM), MD-LSTM, etc. Experiments show that our approach has the best-detection accuracy (98.98%) and training stability. Further, to speed up the inference of MULSAM on edge, the hardware accelerator is implemented on FPGA devices using technologies, such as parallelization, modular, pipeline, and fixed-point quantization. Experiments show that our FPGA-based acceleration scheme has a better-energy efficiency than the CPU platform. Even with a certain degree of quantification, the acceleration model for MULSAM still displays a high-detection accuracy of 98.81% and a low latency of 1.88 ms.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3274-3288"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs","authors":"Wei-Che Cheng;Shih-Hsu Huang;Jin-Fu Li","doi":"10.1109/TCAD.2025.3541483","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541483","url":null,"abstract":"To overcome the von Neumann bottleneck, computing-in-memories (CIMs) have emerged as a design trend. On the other hand, with the globalization of the semiconductor supply chain, hardware Trojans have become a significant security concern. While there have been some studies on hardware Trojan designs for embedded memories in the past, there is no literature addressing hardware Trojan designs for CIMs. In this article, we propose a hardware Trojan design for spin transfer torque magnetoresistive random access memory (STT-MRAM)-based CIMs that can disrupt computing-mode operations. Our trigger circuit can evade detection during post-manufacturing memory testing, and our payload circuit can disrupt over 99% of CIM operations. Experimental results also demonstrate that compared to the original peripheral circuits of STT-MRAM-based CIMs, the area overhead and power overhead (at the TT process corner) caused by our inserted hardware Trojan are only 1.023% and 0.123%, respectively. Therefore, our hardware Trojan can easily hide within the peripheral circuits.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3260-3273"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis","authors":"Boyu Long;Yinhe Han;Xian-He Sun;Xiaoming Chen","doi":"10.1109/TCAD.2025.3541487","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541487","url":null,"abstract":"The reconfigurable processing-in-memory (PIM) architecture has garnered significant attention in recent years due to its versatility and ability to overcome storage limitations. However, it faces challenges, such as overly complex mapping and routing caused by the fine granularity of basic logic units, and the inclusion of numerous redundant devices to achieve reconfigurability. To address these issues, we have designed a software-hardware co-design reconfigurable PIM architecture called Re-Meltrix. Its hardware architecture uses an resistive random-access memory array as the foundation, combined with well-designed peripheral circuits. Maintaining a controllable area, it integrates logic, storage, ternary content-address memory, and interconnection modes into a unified tile architecture and implements two-level independent interconnection within and between tiles. This approach achieves a single tile logic capacity multiple times that of the most advanced reconfigurable PIM architectures currently available, thereby resolving mapping and routing difficulties at the hardware level. Our proposed function synthesis, combined with the hardware architecture, specifically optimizes two-level interconnection separation and module segmentation, further reducing interconnection complexity and improving tile usage efficiency. Experiments have demonstrated that our architecture outperforms the state-of-the-art Liquid Silicon by 2.00–<inline-formula> <tex-math>$4.31times $ </tex-math></inline-formula> in performance and reduces power consumption by 29%–68%. Compared with the previously published Meltrix, the area has decreased by 15%–35%, with the area and power consumption remaining almost unchanged.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3409-3422"},"PeriodicalIF":2.9,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sampling-Biorthogonal Time-Domain Technique for Temperature-Dependent Transient Analysis of Coaxial-TGVs in 3-D Integration","authors":"K. Madhu Kiran;Rohit Dhiman","doi":"10.1109/TCAD.2025.3541011","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541011","url":null,"abstract":"A novel sampling-biorthogonal time-domain (SBTD) technique by considering the positive sampling basis and biorthogonal dual testing functions is developed to accurately model temperature-dependent crosstalk effects in circular and square coaxial-through glass vias (C-TGVs). An equivalent transmission-line model employing EM theory-based Bessel and Neumann functions to establish closed-form formulae for the frequency- and temperature-dependent resistance, inductance, capacitance, and conductance (per-unit-height) of both C-TGV configurations is presented. The efficacy of proposed SBTD technique is verified with SPICE results and conventional finite-difference time-domain (FDTD) technique. The SBTD technique proves more efficient with respect to FDTD, exhibiting less than 0.7% average error in estimating dynamic crosstalk-induced delay with lesser computational effort. Therefore, it is very useful for addressing the issues of electromagnetic interference and electromagnetic compatibility in 3-D integration.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3560-3570"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments","authors":"Na Bai;Fudong Wang;Yaohua Xu;Shaowei Wang;Xiaoqing Wen","doi":"10.1109/TCAD.2025.3541010","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3541010","url":null,"abstract":"This article proposes a novel and effective 14-transistors (14T) reconfigurable radiation-hardened static-random access-memory cell design under the SMIC 65-nm process, featuring a unique memory reconfigurability architecture with two operation modes, namely the high reliability (HR) mode and the triple-time memory (TTM) mode for meeting different radiation environmental requirements. The proposed HR mode provides strong protection of the memory arrays in harsh radiation environments. Compared with the traditional triple modular redundancy (TMR) structure, the proposed HR mode reduces area overhead by 30%, delay by 37%, and power consumption by 16%. The TTM mode uses the enable (EN) circuit to expand the capacity threefold in less harsh radiation environments, avoiding the area wastage caused by the traditional TMR structure. By implementing the two innovative operation modes, the proposed design overcomes the limitations of the traditional TMR structure, reducing area overhead while retaining the radiation hardening capability. In addition, this article presents a mode-switching mechanism composed of a detection circuit and an EN circuit. The detection circuit can detect errors in the reconfigurable architecture. With the proposed mode-switching mechanism, two operation modes can switch in response to different radiation environments. Besides, to ensure the normal operations of the TTM mode in radiation environments, the proposed 14T cell serves as a bitcell in the memory reconfigurable architecture. Compared with typical existing designs, such as radiation-hardened based design, writability enhanced, and dual interlocked storage cell (DICE) cells, the proposed 14T cell design has better delay, critical charge, and higher hold static noise margin.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 9","pages":"3581-3591"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}