IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"Single-Event Transient Analysis on NCringFET Devices and Inverter Circuits Utilizing Numerical Device Simulations","authors":"M. Ramya;K. K. Nagarajan;Kumar Prasannajit Pradhan","doi":"10.1109/TCAD.2025.3609238","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3609238","url":null,"abstract":"The heavy ion radiation performance of NCringFET with single and dual-k spacers using both the inner and outer drain (OD) arrangements are investigated using 3-D technology computer aided design (TCAD) simulations. DC performance parameters, including <sc>on</small> current (<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>), <sc>off</small> current (<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula>), and <inline-formula> <tex-math>${I}_{text {on}}big /{I}_{text {off}}$ </tex-math></inline-formula> ratio, are obtained for all NCringFET structures. The behavior of NCringFET to heavy ion irradiation is analyzed, and the device’s susceptible area is identified via single-event transient (SET) analysis. It was discovered that the most susceptible area for an inner drain (ID) arrangement is the centre of the drain (CD), whereas the most susceptible area for an OD arrangement is the spacer near the drain (SND). The source region (CS) is the least susceptible area for both OD and ID arrangements. Also, the SET performance of NCringFET-based Inverters using both OD and ID arrangements are examined. NCringFET with an ID arrangement exhibits improved performance in radiation-prone areas due to its reduced collected charge, making it a more suitable choice for applications requiring high reliability and radiation tolerance at both the device level and circuit level.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1802-1812"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MarchGen: A March Sequence Generation Method for Faults With an Arbitrary Number of Operations in RAMs","authors":"Sunrui Zhang;Xiaole Cui;Huixian Huang;Feng Wei;Yongliang Chen;Xing Zhang","doi":"10.1109/TCAD.2025.3609248","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3609248","url":null,"abstract":"The March test is a widely applied test method for memory arrays. Nowadays, the advanced memory technologies keep introducing new types of defects, which bring diverse multioperation fault models in turn. The automatic March sequence generation methods are preferred to avoid the inefficient manual design. Most previous methods generate the March sequences that cover limited types of faults and strongly depend on the specific characteristics of known faults. To address this issue, this work proposes MarchGen, a March sequence generation method for memory faults with an arbitrary number of operations. First, the fault hierarchies, reduced taxonomy, and generic test conditions of 2-composite faults are analyzed. Then, the heuristic March sequence generation workflow is designed accordingly, which takes either fault models or test sequences (TSs) as input. Three optimization strategies are utilized to improve the fault coverage of the generated March sequences and the generation time consumption. The evaluation results show that the proposed method has low dependence on fault types. The generated March sequences reach 100% fault coverage for any simple and 2-composite faults or TSs, and the generation time is roughly linear with the size of the input set.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1813-1826"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN","authors":"Jinhoon Hyun;Inchul Jeong;Shinho Chu;Jaemyung Lim","doi":"10.1109/TCAD.2025.3607129","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607129","url":null,"abstract":"In the modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during postphysical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including PDN, ensuring it is suitable for final sign-off. By applying this methodology, the PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1782-1786"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chipletizer 2.0: Toward Cost-Effective Chiplet Design via Reuse-Aware Decomposition","authors":"Fuping Li;Ding Yuan;Yujie Wang;Juelei Zhou;Xihao Liang;Yinhe Han;Huawei Li;Xiaowei Li;Ying Wang","doi":"10.1109/TCAD.2025.3602743","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3602743","url":null,"abstract":"The decomposition-based chiplet design paradigm, which breaks monolithic system-on-chips (SoCs) into smaller chiplets, has proved effective in reducing costs and accelerating development. The vast design space of multichiplet systems necessitates automated techniques to maximize their benefits while minimizing overheads. However, current chiplet decomposition flows lack support for exploring reusable chiplets, missing opportunities to efficiently amortize nonrecurring engineering (NRE) costs. To fully unleash the economic potential of chiplets, we propose <sc>Chipletizer 2.0</small>, a cost-driven framework that guides SoC decomposition and enables chiplet reuse across a line of products. This early-stage chiplet planning framework determines critical system parameters involving the partition, floorplan, and die-to-die (D2D) interface, based on user-specified optimization goals. Experimental results demonstrate that, compared with the existing chiplet decomposition techniques, our proposed framework achieves significant cost improvements on realistic product lines with acceptable overheads.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1584-1597"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation","authors":"Yanjing Wang;Lizhou Wu;Wentao Hong;Yang Ou;Zicong Wang;Sunfeng Gao;Jie Zhang;Sheng Ma;Dezun Dong;Xingyun Qi;Mingche Lai;Nong Xiao","doi":"10.1109/TCAD.2025.3607145","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607145","url":null,"abstract":"Compute Express Link (CXL) has emerged as a key enabler of memory disaggregation for future heterogeneous computing systems to expand memory on demand and improve resource utilization. However, CXL is still in its infancy stage and lacks commodity products on the market, thus necessitating a reliable system-level simulation tool for research and development. In this article, we propose CXL-DMSim (open-sourced at <uri>https://github.com/ferry-hhh/CXL-DMSim</uri>), an open-source full-system (FS) simulator to simulate CXL disaggregated memory systems with high fidelity at a gem5-comparable simulation speed. CXL-DMSim incorporates a flexible CXL memory expander model along with its associated device driver, and CXL protocol support with CXL.io and CXL.mem. It can operate in both the app-managed (AM) mode and the kernel-managed (KM) mode, with the latter using a dedicated NUMA-compatible mechanism. The simulator has been rigorously verified against a real hardware testbed with both FPGA- and ASIC-based CXL memory devices, which demonstrates the qualification of CXL-DMSim in simulating the characteristics of various CXL memory devices at an average simulation error of 3.4%. The experimental results using LMbench and STREAM benchmarks suggest that the CXL-FPGA memory exhibits a <inline-formula> <tex-math>$sim 2.88times $ </tex-math></inline-formula> higher latency than local DDR, while the CXL-ASIC latency is <inline-formula> <tex-math>$sim 2.18times $ </tex-math></inline-formula>; CXL-FPGA achieves 45%–69% of local DDR memory bandwidth, whereas the number for CXL-ASIC is 82%–83%. The study also reveals that CXL memory can significantly enhance the performance of memory-intensive applications, improving by <inline-formula> <tex-math>$23times $ </tex-math></inline-formula> at most with limited local memory for Viper key–value database and approximately 60% in memory-bandwidth-sensitive scenarios such as MERCI. Moreover, the simulator’s observability and expandability are showcased with detailed case studies, highlighting its great potential for research on future CXL-interconnected hybrid memory pools.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1787-1801"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic Binary Translation of VLIW Code With Software Pipeline","authors":"Hongliang Liang;Kailai Liao;Guohao Wu;Qiuping Yi","doi":"10.1109/TCAD.2025.3604316","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3604316","url":null,"abstract":"Dynamic binary translation (DBT) serves as a pivotal technique for instruction set simulation, yet encounters critical challenges when handling explicit instruction-level parallelism (ILP) and operational latency inherent in very long instruction word (VLIW) architectures. Existing approaches demonstrate limited capability in handling nonarithmetic operations, particularly branch and memory access instructions. The complexity intensifies when translating software-pipelined loops featuring architecture-specific instructions due to two inherent characteristics: 1) instruction reordering, overlapping, and masking within loop bodies, and 2) absence of explicit conditional branches and loop counter manipulation instructions. This work presents three original strategies for VLIW code translation. First, a strategy constrains the translation block (TB) length to resolve branch instruction challenges. Second, an approach manages store-load dependencies through the strategic postponement of store instruction processing. Third, a novel software-pipelined loop translation methodology ensures correct execution semantics by serializing parallel iterations, generating state-specific TBs, and synchronizing inner and outer loops translations. We implemented these techniques in VEMU and evaluated it against dsplib and Polybench benchmarks. VEMU successfully translates all benchmark programs. Our first strategy does not degrade performances and the second strategy brings 0.2% time overhead. Comparative analysis reveals a speedup ratio between <inline-formula> <tex-math>$3.25times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$7times $ </tex-math></inline-formula> over the Texas Instruments simulator for the same benchmarks, validating the efficacy of the proposed techniques.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1751-1763"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Event-Based Simulation of Stochastic Memristive Devices for Neuromorphic Computing","authors":"Waleed El-Geresy;Christos Papavassiliou;Deniz Gündüz","doi":"10.1109/TCAD.2025.3607670","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3607670","url":null,"abstract":"In this article, we build a general modeling framework for memristors, suitable for the simulation of event-based systems such as hardware spiking neural networks, and more generally, neuromorphic computing systems composed of three independent components: 1) an event-based modeling approach, extending and generalizing an existing general model of memristors—the generalized metastable switch model (GMSM)—eliminating errors associated with discrete time approximation, as well as offering potential improvements in terms of suitability for neuromorphic memristive system simulations; 2) a volatility state variable to allow for the unified understanding of disparate nonlinear and volatile phenomena, including state relaxation, structural disruption, Joule heating, and nonlinear drift in different memristive devices; and 3) a readout equation that separates the latent state variable evolution from explicit variables of interest such as an instantaneous resistance. We exhibit an illustrative implementation of this framework, fit to a resistive drift dataset for titanium dioxide memristors, based on a proposed linear conductance model for resistive drift in the devices. Finally, we highlight the application of the model to neuromorphic computing by demonstrating the contribution of the volatility state variable to switching dynamics, resulting in frequency-dependent switching (for stable memristors acting as programmable synaptic weights) and the generation of action potentials (for unstable memristors, acting as spike generators).","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 4","pages":"1635-1648"},"PeriodicalIF":3.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Redefining Tradition: An Active Watermarking Approach for IP Protection in SoCs","authors":"Zahin Ibnat;Mridha Md Mashahedur Rahman;Sazadur Rahman;Jingbo Zhou;Farimah Farahmandi","doi":"10.1109/TCAD.2025.3611871","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3611871","url":null,"abstract":"Globalization of the system-on-chip (SoC) supply chain has resulted in increased intellectual property (IP) piracy, illegal reuse, and tampering by malicious actors. In response to these challenges, IP watermarking presents itself as a promising solution to protect against these risks; however, traditional methods rely heavily on labor-intensive manual tests by verification engineers and fail to account for the potential threat posed by malicious SoC design houses. To overcome these challenges and improve the efficiency of the watermark verification process while safeguarding against possible attacks, we developed ActiWate as an innovative watermarking approach that not only provides proof of authorship but also prevents unauthorized usage of an IP. Using an automatic self-verification technique, the watermark establishes communication with various peripherals within the SoC. The versatility and effectiveness of ActiWate have been proven through extensive experiments on multiple SoCs with diverse components and peripherals, including the testing of watermarking and the verification of various IPs. Moreover, we discuss the inclusion of this multiple serialized verification in more case studies and results, as well as analyzing prominent security threats, including reverse engineering attacks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2517-2530"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Instruction Fusion for ASIPs: A Low-Cost Approach to Structural Hazard Control","authors":"Xinbing Zhou;Tianlang Liu;Tiancheng Tang;Yi Man;Peng Hao;Wei Chen;Dake Liu","doi":"10.1109/TCAD.2025.3611113","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3611113","url":null,"abstract":"Moore’s law is reaching saturation, while the demand for computing capacity continues to rise. Application-Specific Instruction-set Processor (ASIPs) is therefore an essential technology for embedded processing in areas such as communication, media, gaming, and control systems, due to its high area and energy efficiency. The most effective method for ASIPs acceleration is known as instruction fusion. Instruction fusion enhances performance but also introduces challenges related to the complexity of structural hazard control. The difficulty in this research field is achieving fine-grained structural hazard control using low-cost hardware. The state-of-the-art technologies have not been able to effectively address this challenge. First, this article systematically analyzes the rationale behind instruction fusion and explores methods to optimize its performance. Second, based on the design of a 5G micro base station baseband processor, we present an instruction fusion pipeline design example. Furthermore, to address the structural hazards that arise from instruction fusion, we propose a lightweight hardware resource table (HRT) to address the issue and outline its benefits. These benefits include utilizing low silicon costs to achieve performance improvements and reducing on-chip program memory. According to benchmark evaluations, area efficiency improves by 23%, accompanied by a 108% increase in energy efficiency.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2418-2431"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Electronically Tunable Dual Flux-Controlled Floating Memristor Emulator","authors":"Navnit Kumar;Neeta Pandey;Manjeet Kumar;Manish Kumar;Shahram Minaei","doi":"10.1109/TCAD.2025.3610736","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3610736","url":null,"abstract":"In recent years, memristor emulators have been used in a wide range of applications including neuromorphic computing, security, analog signal processing, and other related fields. This article introduces a novel electronically tunable dual flux-controlled floating memristor emulator using single current-controlled differential difference current conveyor (CCDDCC), a MOS capacitor, and one pMOS transistor. The core of the suggested emulator features an electronically tunable CCDDCC-based feedback circuit. The proposed circuit avoids passive components, diodes, and analog multiplier circuits. The suggested memristor has the ability to tune the area of the pinch hysteresis loop (PHL) without altering the input frequency, input voltage, MOS capacitance, and active component. The circuit operates effectively within a 300-MHz frequency range and demonstrates a well-defined pinched hysteresis loop. Its performance is evaluated using 180-nm TSMC parameters, with a compact layout area of <inline-formula> <tex-math>$758.12~mu $ </tex-math></inline-formula> m2. In addition, the robustness of the circuit is thoroughly assessed through analyses of temperature variations, supply voltage fluctuations, transistor size variations, and process corner simulations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2085-2094"},"PeriodicalIF":3.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}