IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

Redefining Tradition: An Active Watermarking Approach for IP Protection in SoCs 重新定义传统：用于soc中知识产权保护的主动水印方法

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-18 DOI: 10.1109/TCAD.2025.3611871

Zahin Ibnat;Mridha Md Mashahedur Rahman;Sazadur Rahman;Jingbo Zhou;Farimah Farahmandi

{"title":"Redefining Tradition: An Active Watermarking Approach for IP Protection in SoCs","authors":"Zahin Ibnat;Mridha Md Mashahedur Rahman;Sazadur Rahman;Jingbo Zhou;Farimah Farahmandi","doi":"10.1109/TCAD.2025.3611871","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3611871","url":null,"abstract":"Globalization of the system-on-chip (SoC) supply chain has resulted in increased intellectual property (IP) piracy, illegal reuse, and tampering by malicious actors. In response to these challenges, IP watermarking presents itself as a promising solution to protect against these risks; however, traditional methods rely heavily on labor-intensive manual tests by verification engineers and fail to account for the potential threat posed by malicious SoC design houses. To overcome these challenges and improve the efficiency of the watermark verification process while safeguarding against possible attacks, we developed ActiWate as an innovative watermarking approach that not only provides proof of authorship but also prevents unauthorized usage of an IP. Using an automatic self-verification technique, the watermark establishes communication with various peripherals within the SoC. The versatility and effectiveness of ActiWate have been proven through extensive experiments on multiple SoCs with diverse components and peripherals, including the testing of watermarking and the verification of various IPs. Moreover, we discuss the inclusion of this multiple serialized verification in more case studies and results, as well as analyzing prominent security threats, including reverse engineering attacks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2517-2530"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Instruction Fusion for ASIPs: A Low-Cost Approach to Structural Hazard Control 高效指令融合：一种低成本的结构危害控制方法

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-17 DOI: 10.1109/TCAD.2025.3611113

Xinbing Zhou;Tianlang Liu;Tiancheng Tang;Yi Man;Peng Hao;Wei Chen;Dake Liu

{"title":"Efficient Instruction Fusion for ASIPs: A Low-Cost Approach to Structural Hazard Control","authors":"Xinbing Zhou;Tianlang Liu;Tiancheng Tang;Yi Man;Peng Hao;Wei Chen;Dake Liu","doi":"10.1109/TCAD.2025.3611113","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3611113","url":null,"abstract":"Moore’s law is reaching saturation, while the demand for computing capacity continues to rise. Application-Specific Instruction-set Processor (ASIPs) is therefore an essential technology for embedded processing in areas such as communication, media, gaming, and control systems, due to its high area and energy efficiency. The most effective method for ASIPs acceleration is known as instruction fusion. Instruction fusion enhances performance but also introduces challenges related to the complexity of structural hazard control. The difficulty in this research field is achieving fine-grained structural hazard control using low-cost hardware. The state-of-the-art technologies have not been able to effectively address this challenge. First, this article systematically analyzes the rationale behind instruction fusion and explores methods to optimize its performance. Second, based on the design of a 5G micro base station baseband processor, we present an instruction fusion pipeline design example. Furthermore, to address the structural hazards that arise from instruction fusion, we propose a lightweight hardware resource table (HRT) to address the issue and outline its benefits. These benefits include utilizing low silicon costs to achieve performance improvements and reducing on-chip program memory. According to benchmark evaluations, area efficiency improves by 23%, accompanied by a 108% increase in energy efficiency.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2418-2431"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Securing Storage Instructions: A Hamming Weight Balancing Approach to Prevent Secret Leaks Through Side Channels 安全存储说明：一个汉明重量平衡方法，以防止秘密泄漏通过侧通道

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-24 DOI: 10.1109/TCAD.2025.3614099

Jianfeng Du;Zhu Wang;Aimin Yu

引用次数: 0

A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication 可靠稀疏矩阵乘法的故障感知体系结构

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-10-07 DOI: 10.1109/TCAD.2025.3618934

Yifan Song;Yuxuan Qiao;Changxu Liu;Yifei Feng;Junjie Zuo;Baoyu Fan;Fan Yang

{"title":"A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication","authors":"Yifan Song;Yuxuan Qiao;Changxu Liu;Yifei Feng;Junjie Zuo;Baoyu Fan;Fan Yang","doi":"10.1109/TCAD.2025.3618934","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3618934","url":null,"abstract":"With the advancement of artificial intelligence (AI), the reliability of AI accelerators has become increasingly critical. Moreover, sparse matrix multiplication has become a fundamental primitive of deep learning, which can enhance the efficiency of model training and inference. However, reduced redundancy in sparse pruning models increases their vulnerability to permanent faults. Thus, ensuring both efficiency and reliability in sparse matrix multiplication is critical. Most existing reliable AI accelerators are tailored for general matrix multiplication, leading to suboptimal efficiency when handling sparse matrix multiplication and incurring substantial hardware overhead to support fault tolerance. To address this, we propose a hardware–software co-design fault-aware architecture for reliable sparse matrix multiplication, with negligible additional area overhead. Specifically, based on the unstructured-pruned matrix, we propose fault-aware reordering for a sparse matrix at the algorithmic level, which mitigates faults through fine-grained data scheduling and further enables parallel computation by employing a sparsity-aware merging strategy. At the hardware level, we design a fault-tolerant sparse matrix accelerator based on an optimized systolic array for sparse matrices, incorporating bypass paths for faulty PEs. Experimental results demonstrate that our architecture can tolerate a fault rate of up to <inline-formula> <tex-math>$boldsymbol {10%}$ </tex-math></inline-formula>, achieving a recovery efficiency improvement of <inline-formula> <tex-math>$boldsymbol {1.89times !!! sim !! 7.11 times }$ </tex-math></inline-formula> compared to existing methods, with minimal area overhead.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2395-2408"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RCNet: ΔΣ IADCs as Recurrent AutoEncoders RCNet： ΔΣ作为循环自动编码器的iadc

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-11 DOI: 10.1109/TCAD.2025.3609242

Arnaud Verdant;William Guicquero;Jérôme Chossat

{"title":"RCNet: ΔΣ IADCs as Recurrent AutoEncoders","authors":"Arnaud Verdant;William Guicquero;Jérôme Chossat","doi":"10.1109/TCAD.2025.3609242","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3609242","url":null,"abstract":"This brief proposes a deep learning model [recurrent conversion network (RCNet)] for delta–sigma (<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>) analog-to-digital converters (ADCs). Recurrent neural networks (RNNs) allow to describe both modulators and filters. This analogy is applied to incremental <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADC (IADC). High-end optimizers combined with full-custom losses are used to define additional hardware design constraints: quantized weights, signal saturation, temporal noise injection, devices area, capacitor mismatch, and finite-gain amplifier. Focusing on dc conversion, our early results demonstrate that signal-to-noise ratio (SNR) defined as an effective number of bits (ENOB) can be optimized under a certain hardware mapping complexity. The proposed RCNet succeeded to provide design tradeoffs in terms of SNR (>13 bits) versus area constraints (<14-pF> <tex-math>$1% cdot mu text {m}$ </tex-math></inline-formula> mismatch) at a given oversampling ratio (OSR) (80 samples). Interestingly, it appears that the best RCNet architectures do not necessarily rely on high-order modulators, leveraging additional topology exploration degrees of freedom.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2390-2394"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Graphic Leakage Structure for the Formal Verification of Composite ISW Masking Circuits 一种用于复合ISW掩蔽电路形式化验证的新型图形泄漏结构

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-22 DOI: 10.1109/TCAD.2025.3612867

Yu Ou;Yongzhuang Wei

{"title":"A Novel Graphic Leakage Structure for the Formal Verification of Composite ISW Masking Circuits","authors":"Yu Ou;Yongzhuang Wei","doi":"10.1109/TCAD.2025.3612867","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3612867","url":null,"abstract":"The hardware security of cryptographic devices has emerged as a matter of significant concern. To protect these devices against side channel attacks, the Ishai, Sahai, and Wagner (ISW) masking scheme was proposed to conceal sensitive data involved in <sc>xor</small> gate and <sc>and</small> gate operations in the circuit. Subsequently, numerous formal verification tools based on the t-probing model have been suggested to determine the security of circuits. In particular, both tightPROVE and Tornado are capable of directly assessing whether circuits meet the t-probing security. However, these tools encounter increased processing times when dealing with complex, large-scale circuits, as they necessitate a comprehensive scan of the entire circuit. In contrast, this article introduces a novel approach that visualizes composite ISW circuits and reevaluates the leakage of features within graph structures. More precisely, a new leakage structure is delineated by representing circuits as directed graphs. The theoretical underpinnings of this leakage structure and its potential extensions are explored, offering a direct method to validate the security of ISW masking circuits. Furthermore, a dataset of ISW masking circuits and an algorithm for its generation are presented. Three machine learning (ML) methods are utilized to perform an experiment on the dataset. The results demonstrate that the highest classification accuracy is attained at 99%, with a significant enhancement in efficiency (71%) compared to the performance of both tightPROVE and Tornado.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2507-2516"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

REEG: Reinforcement Learning-Based Gang Scheduling in Multicore Embedded Systems 多核嵌入式系统中基于强化学习的队列调度

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-10-06 DOI: 10.1109/TCAD.2025.3616847

Majid Hajilou;Mohsen Ansari

{"title":"REEG: Reinforcement Learning-Based Gang Scheduling in Multicore Embedded Systems","authors":"Majid Hajilou;Mohsen Ansari","doi":"10.1109/TCAD.2025.3616847","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3616847","url":null,"abstract":"In modern cyber-physical systems (CPSs), the increasing complexity and parallel execution demands of applications necessitate adopting advanced task scheduling and task orchestration models to optimize system performance and resource allocation in multicore systems. In this brief, we present a novel task model and its corresponding RL-based algorithm, named reinforcement learning-based energy-efficient gang scheduling (REEG) in multicore CPSs, in which each node of a directed acyclic graph (DAG) is characterized as a gang task, requiring simultaneous execution across multiple cores, thus offering a precise and scalable framework for optimizing the performance of complex, highly parallel workloads in modern multicore systems. However, significant energy optimization challenges exist due to the complex dependencies and simultaneous core usage. We propose a framework based on reinforcement learning (RL) that dynamically modifies core allocation and execution techniques to reduce energy consumption and maintain computational efficiency without compromising QoS or performance. This approach reduces energy consumption while maintaining performance and QoS, ensuring efficient computation. Our experimental results demonstrate that the RL-based method achieves notable energy reductions and improves system efficiency compared to the state-of-the-art method. On average, our proposed method (REEG) achieves 28.19% less energy consumption and 60.75% more QoS compared to the state-of-the-art methods.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2474-2478"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information IEEE集成电路与系统计算机辅助设计汇刊

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2026-04-22 DOI: 10.1109/TCAD.2026.3681420

引用次数: 0

Safe Reinforcement Learning for NN-Controlled Systems With Neural Barrier Certificate Guidance 神经屏障证书指导下神经控制系统的安全强化学习

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-10-01 DOI: 10.1109/TCAD.2025.3616856

Hanrui Zhao;Mengxin Ren;Banglong Liu;Niuniu Qi;Xia Zeng;Zhenbing Zeng;Zhengfeng Yang

{"title":"Safe Reinforcement Learning for NN-Controlled Systems With Neural Barrier Certificate Guidance","authors":"Hanrui Zhao;Mengxin Ren;Banglong Liu;Niuniu Qi;Xia Zeng;Zhenbing Zeng;Zhengfeng Yang","doi":"10.1109/TCAD.2025.3616856","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3616856","url":null,"abstract":"Safe controller synthesis is crucial for safety-critical applications. This article presents a novel reinforcement learning (RL) approach to synthesize safe controllers for neural network (NN)-controlled systems. The core idea leverages an iterative scheme that combines controller learning with neural barrier certificate (BC) verification, ultimately producing a provably safe deep neural network (DNN) controller with formal safety guarantees. The process begins by pretraining a well-performing DNN controller as an “oracle” via deep RL (DRL). To formally verify the safety properties of the closed-loop system under the base controller, we devise a formal verification procedure that approximates the DNN controller using polynomial inclusion, followed by synthesizing neural BCs via sum-of-squares (SOS) relaxation. In cases where the base controller is insufficient to yield a real BC, the current spurious BC is incorporated as an additional penalty term to reshape the RL reward function, guiding the iterative refinement for new controllers. We implement an automated tool, neural BC-guided safe RL NBCRL, and experimental results demonstrate the benefits of our method in terms of efficiency and scalability even for a nonlinear system with a dimension up to 12.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2460-2473"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Registry: Enhancing Vertex Reusability for GCN Inference on Hybrid Stacked Memory 注册表：增强混合堆叠内存上GCN推理的顶点可重用性

IF 2.9 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2026-03-01 Epub Date: 2025-09-22 DOI: 10.1109/TCAD.2025.3612868

Zhaoyu Zhong;Jiaxian Chen;Yunhao Dong;Tianyu Wang;Chenlin Ma;Rui Mao;Yi Wang

{"title":"Registry: Enhancing Vertex Reusability for GCN Inference on Hybrid Stacked Memory","authors":"Zhaoyu Zhong;Jiaxian Chen;Yunhao Dong;Tianyu Wang;Chenlin Ma;Rui Mao;Yi Wang","doi":"10.1109/TCAD.2025.3612868","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3612868","url":null,"abstract":"Graph convolutional networks (GCNs) have emerged as a powerful paradigm for analyzing graph-structured data across diverse domains. The irregular memory access patterns and complex topology of real-world graphs pose significant challenges for efficient GCN processing on conventional hardware architectures. 3-D-stacked processing-in-memory (PIM) architectures offer promising solutions through reduced data movement and high bank-level bandwidth. However, existing PIM-based GCN accelerators still suffer from redundant data movement due to suboptimal hardware/software co-design. This article presents Registry, a novel GCN accelerator that effectively integrates hardware and software optimizations within a 3-D PIM architecture. At the hardware level, Registry introduces a hybrid design with two types of processing units: near-bank processing units for sparse graph operations and a dedicated processing unit on the base die for intensive computations. At the software level, Registry develops a vertex reusability metric that guides graph partitioning and workload mapping. This metric-driven partitioning strategy enables optimized workload mappings across processing units, effectively reducing interpartition data movement. The experimental evaluation shows that Registry achieves significant speedups, reduces energy consumption, and improves vertex reusability compared with representative schemes.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 5","pages":"2376-2389"},"PeriodicalIF":2.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147732974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0