IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2026.3700374","DOIUrl":"https://doi.org/10.1109/TCAD.2026.3700374","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"C2-C2"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11573129","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intertwine: Nonlinear Quantum Feature Selection With Multikernel Circuits","authors":"Hang Xu;Jiaye Li","doi":"10.1109/TCAD.2025.3635568","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3635568","url":null,"abstract":"Feature selection accelerates training, enhances interpretability, and reduces data dimensionality by identifying the most relevant and important features, thereby improving machine learning performance. However, current quantum feature selection (QFS) methods are still in their early stages and predominantly focus on linear relationships within the data. This limitation overlooks potential nonlinear relationships, preventing the selection of the most representative feature subset. Consequently, this shortcoming can degrade the performance of subsequent learning tasks, especially on nonlinear datasets. To address this challenge, we propose Intertwine, a nonlinear quantum feature selection method with multikernel circuits. Specifically, we design a quantum multikernel circuit that independently maps each feature, enabling the extraction of multiple kernel matrices. This process maps all features into the quantum kernel space, where the original nonlinear relationships become linearly separable, effectively capturing the inherent nonlinear structure in the data. We then construct a nonlinear feature selection objective function by incorporating class labels, kernel matrices, and orthogonality constraints to guide the selection process. Finally, we validate the effectiveness of Intertwine on both synthetic and public datasets. Experimental results demonstrate that Intertwine outperforms state-of-the-art QFS methods, achieving an average improvement of 4.60% in classification accuracy. The source code for the proposed Intertwine method is publicly available at <uri>https://github.com/xhchangsha/quantum-feature-selection</uri>","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3346-3359"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"UniSparTa: A Unified Sparse Tensor Program Tuning Framework","authors":"Zihan Wang;Lei Gong;Xiangjun Qu;Cheng Tang;Wenqi Lou;Teng Wang;Qianyu Cheng;Xianglan Chen;Chao Wang;Xuehai Zhou","doi":"10.1109/TCAD.2025.3636442","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3636442","url":null,"abstract":"Sparse tensor computation is widely used in deep learning and scientific computing. However, diverse sparse data and algorithmic characteristics at the application level, combined with the diversity of hardware platforms, pose significant challenges for efficient sparse tensor program optimization. Manually crafted operator libraries are time-consuming to develop and lack portability. To address this, we propose UniSparTa, a unified sparse tensor program tuning framework that automatically generates high-performance programs. First, we extract unified optimization principles for high-performance sparse tensor programs and propose a domain-specific language (DSL) to automatically generate a high-quality design space without manual intervention. Second, by analyzing the general distribution of the design space, we introduce an adaptive search strategy combining deep <inline-formula> <tex-math>$Q$ </tex-math></inline-formula>-networks (DQNs) and simulated annealing (SA). Finally, to avoid the unacceptable time cost of real measurement during tuning, we propose a unified cost model based on multimodal fusion to accurately predict program performance. Furthermore, by leveraging data augmentation and transfer learning, we enable low-cost transfer prediction across different sparse data patterns, algorithms, and hardware platforms. Results show that, compared with the state-of-the-art operator library MKL, the manually optimized scheme ASpT, the tensor compiler TVM, and the sparse tensor tuning framework WACO, UniSparTa achieves average speedups of <inline-formula> <tex-math>$1.98times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$2.75times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$6.13times $ </tex-math></inline-formula>, and <inline-formula> <tex-math>$1.75times $ </tex-math></inline-formula>, respectively. Moreover, UniSparTa significantly accelerates the tuning process.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3360-3373"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PMTV PUF: Power-Aware and ML-Secure PUF With Tolerance to Temperature and Voltage Fluctuations","authors":"Abolfazl Rajaiyan;Yas Hosseini Tehrani;Seyed Mojtaba Atarodi","doi":"10.1109/TCAD.2025.3634304","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3634304","url":null,"abstract":"Security of data transmission is one of the main challenges in the Internet of Things (IoT) networks. One of the main solutions to ensure security in these networks is physically unclonable functions (PUFs). The performance of the PUFs is highly dependent on voltage and temperature. Moreover, this solution can be successfully attacked by machine learning (ML) approaches. Detecting the possibility of an attack helps in preventing it. In this article, a novel PUF (PMTV PUF) is presented. The proposed circuit uses a pipeline structure. This structure improves the reliability of the PUF under different voltages and temperatures. Pipeline architecture is also used to resist ML attacks. Challenge obfuscation is applied in the pipeline stages. This makes it harder for ML models to learn the behavior. In addition, new techniques for measuring system power consumption are used. These techniques help detect and prevent potential ML attacks. The proposed PMTV PUF circuit is implemented on a Xilinx Zynq 7 FPGA with the proposed power measurement circuit as an extension. Experimental results show the great performance of the responses. The bit error rate (BER) is <inline-formula> <tex-math>$3.17 times 10^{-10}$ </tex-math></inline-formula> (at <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C with a 1.32-V supply voltage), the uniformity is 50.12%, and the uniqueness is 49.87%. In conventional architectures, the average system vulnerability against ML attacks is approximately <inline-formula> <tex-math>$mathbf {9 0 %}$ </tex-math></inline-formula>. In the proposed architecture, this vulnerability has been reduced to 50.23%. According to the obtained result, the proposed system not only has high reliability but also possesses the ability to detect and prevent potential ML attacks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3540-3548"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hierarchical-ISA Supporting Row-Wise Operands for Efficient DNN Computation","authors":"Zhiwang Huo;Wenzhe Zhao;Qiwei Dang;Chengyu Ma;Guoming Yang;Gelin Fu;Tian Xia;Pengju Ren","doi":"10.1109/TCAD.2025.3637162","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3637162","url":null,"abstract":"Deep neural networks (DNNs) have become a cornerstone in advancing artificial intelligence, but their complexity often leads to inefficient hardware utilization due to varying structure characteristics and excessive memory accesses. Domain-specific architectures (DSAs) offer a solution by optimizing data locality through data stationarity, tiling, and layer fusion, which minimize memory access and energy consumption while boosting performance. However, current approaches lack flexibility for efficient memory management at the appropriate granularity, causing misaligned accesses and decreasing reuse potential for variable-sized tiles. To this end, we propose a hierarchical instruction set architecture (hierarchical-ISA) combining a RISC-V ISA and a flexible CISC-style macro-ISA (mISA). Unlike byte-level RISC-V, mISA employs row-wise tiles as the fundamental operand, enabling efficient data reuse across adjacent iterations as well as residual connections. This mISA approach simplifies DNN programming, enhances data partitioning and manipulation efficiency, and enables a hardware–software co-designed Remapping mechanism that facilitates data reuse without physical data movement. Experiments show 31.8%–72.0% reductions in off-chip memory access across MobileNet, ResNet, Swin Transformer, and MobileViT, along with speedups of <inline-formula> <tex-math>$2.9times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$7.4times $ </tex-math></inline-formula> compared to previous DNN accelerators. We also conduct comparisons under the roofline model with NVIDIA RTX A6000 and Intel Core i7-10700K. The results show that our arithmetic intensity (AI) reaches up to <inline-formula> <tex-math>$26.0times $ </tex-math></inline-formula> that of i7-10700K and <inline-formula> <tex-math>$22.6times $ </tex-math></inline-formula> that of A6000.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3388-3400"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resolving Gray Code Dilemma With Bidirectional Programming for Efficient QLC SSDs","authors":"Yi Wang;Shaoqi Li;Yongbiao Zhu;Tianyu Wang;Chenlin Ma;Rui Mao;Zili Shao","doi":"10.1109/TCAD.2025.3637010","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3637010","url":null,"abstract":"Quad-level cell (QLC)NAND flash is widely adopted in modern storage systems. By trading off read/write performance for storage density through a “time-for-space” approach, QLC enables ultrahigh storage capacity. To mitigate performance degradation, Gray code and the two-step programming (TSP) algorithm are used. However, Gray code also has limitations: multiple Gray codes (MGCs) incur circuit overhead, while a single Gray code causes extra I/O latency overhead. This paradox seems unsolvable at first glance, requiring an innovative solution that maintains I/O performance without additional circuit overhead. A promising solution lies in selecting an appropriate Gray code and preventing hot data placement on slow physical pages. This article proposes BDP, a novel bidirectional programming scheme that adopts a single Gray code to fit both traditional (forward) and reverse programming directions based on TSP. The objective of BDP is to resolve the inherent contradiction between I/O performance preservation and implementation overhead. BDP optimizes the system performance through hardware/software co-design. At the hardware level, a fixed Gray code is employed to avoid additional circuit complexity. At the software level, two strategies (i.e., hotness-aware data allocation and background data migration) are proposed to further mitigate the misplacement of hot data on slow pages in QLC solid state drives (SSDs). The experimental results demonstrate that BDP significantly reduces the allocation of hot data to slow pages and enhances overall I/O performance compared with representative schemes.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3401-3414"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ConvGA: Convolution Network-Guided Genetic Algorithm for Optimal PDN Decoupling Design","authors":"Yuchuan Lin;Ning Xu;Wei W. Xing;Yuanqing Cheng","doi":"10.1109/TCAD.2025.3635565","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3635565","url":null,"abstract":"Power supply noise has emerged as a critical bottleneck in modern integrated circuit design, where increasing current densities and higher operating frequencies pose significant challenges to system reliability. While decoupling capacitors (decaps) serve as the primary solution for suppressing power delivery network (PDN) noise, determining their optimal values and placement remains computationally prohibitive using traditional methods. This article introduces ConvGA, a novel framework that seamlessly integrates convolutional neural networks (CNNs) with genetic algorithms (GAs) to revolutionize PDN decap optimization. At the heart of ConvGA is a specialized CNN architecture trained on comprehensive boundary element method (BEM) simulations, enabling ultrafast impedance prediction for arbitrary PCB configurations. Our CNN achieves remarkable accuracy while reducing impedance computation time from hours to mere milliseconds—a <inline-formula> <tex-math>$500times $ </tex-math></inline-formula> speedup over conventional BEM calculations. This acceleration enables the GA to efficiently explore vast design spaces through adaptive population control and dynamic constraint mechanisms, systematically minimizing both the number of required capacitors and the deviation from target impedance. Extensive experiments on industrial-scale PDNs demonstrate that ConvGA achieves a <inline-formula> <tex-math>$15times $ </tex-math></inline-formula> reduction in optimization time while requiring 30% fewer capacitors compared to state-of-the-art methods, consistently producing high-quality solutions across diverse PDN configurations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3252-3263"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MFrodo: Efficient and Memory-Sensitive Simulink Code Generation via Redundancy Elimination","authors":"Zehong Yu;Yixiao Yang;Zhuo Su;Haowei Qiu;Rui Wang;Aiguo Cui;Zhan Shu;Yu Jiang","doi":"10.1109/TCAD.2025.3628786","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3628786","url":null,"abstract":"Simulink has emerged as the fundamental infrastructure that supports modeling, simulation, verification, and code generation for embedded software development. To improve the performance of the code generated from Simulink models, state-of-the-art code generators employ various optimization techniques, such as expression folding, variable reuse, and parallelism. However, they overlook the presence of redundant calculations within data-intensive models widely used to perform substantial data processing in embedded scenarios, which can significantly degrade the performance and introduce additional memory usage. This article proposes <sc>MFrodo</small>, an efficient and memory-sensitive code generator for data-intensive Simulink models through redundancy elimination. <sc>MFrodo</small> begins by conducting model analysis to construct the dataflow graph and derive the input/output (I/O) mapping of each block. Then, for each block within the dataflow graph, <sc>MFrodo</small> recursively determines its calculation range by leveraging the I/O mapping of its subsequent blocks and marks optimization blocks whose calculation range is eliminated. For optimizable blocks, <sc>MFrodo</small> eliminates the redundant calculations and reduces the memory space associated with these calculations. Finally, <sc>MFrodo</small> rebuilds the I/O mappings of these optimizable blocks to ensure code correctness and synthesizes the embedded code for deployment. We implemented and evaluated <sc>MFrodo</small> on benchmark Simulink models, in terms of execution duration, memory usage, and code generation overhead across different compilers and architectures. The results show that, compared with the Simulink Embedded Coder, DFSynth, and HCG, <sc>MFrodo</small> achieves performance improvements ranging from <inline-formula> <tex-math>$1.17times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$8.55times $ </tex-math></inline-formula>, while reducing BSS segment usage by 12.00%–52.71%. Besides, <sc>MFrodo</small> reduces compile time by 91.8%–98.7% and code synthesis time by 94.3%–99.6% compared with Simulink Embedded Coder, while incurring comparable overhead to DFSynth and HCG.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3455-3468"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scaling-Free CORDIC Optimization Based on the Time-Multiplexed Constant Multiplication","authors":"Hao Sun;Yu Peng;Xuejing Wei;Liansheng Liu","doi":"10.1109/TCAD.2025.3629615","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3629615","url":null,"abstract":"Modern digital systems in communication, control, and sensing rely on fast and accurate hardware evaluation of trigonometric functions. The classic coordinate rotation digital computer (CORDIC) algorithm provides a multiplier-less solution using iterative shifts and adds, but conventional CORDIC requires many iterations and a final scaling correction that increases latency and hardware cost. The scaling-free CORDIC (SF-CORDIC) eliminates the scaling factor by adjusting micro-rotation angles to achieve a net gain of unity. However, this approach introduces fixed constant multiplications at each iteration, which can dominate hardware resources and critical path delay. Existing methods often restrict the set of rotation angles so that constants can be implemented with simple add–shift operations. Other approaches use high-radix or hybrid schemes, but these methods limit the angle accuracy, introduce extra complexity, and still rely on numerous add–shift networks. To address these issues, a new SF-CORDIC architecture is proposed to eliminate per-iteration multipliers by using the time-multiplexed constant multiplier units implemented across all iterations. Bit-width growth is controlled via shift propagation and a minor compensation step, maintaining precision without a final scaling stage. This compact, low-latency design significantly reduces hardware area and delay compared to prior SF-CORDIC implementations while preserving high output accuracy. In a six-stage FPGA pipeline, the design reaches a maximum clock frequency of 216.03 MHz with an end-to-end latency of 27.78 ns. It uses about 1200 LUTs and 300 registers. The root-mean-square error is <inline-formula> <tex-math>$6.8 times 10^{-5}$ </tex-math></inline-formula> for sine and <inline-formula> <tex-math>$6.4 times 10^{-5}$ </tex-math></inline-formula> for cosine.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3333-3345"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RollPlace: Improving Macro Placement via Monte Carlo Rollout Search","authors":"Qi Zhou;Guojun Liu;Guangzhi Qi;Ming Lu;Jiechu Liu;Zhongli Liu;Jianqun Yang;Xingji Li","doi":"10.1109/TCAD.2025.3635566","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3635566","url":null,"abstract":"The application of reinforcement learning (RL) in electronic design automation (EDA), particularly for chip placement, has attracted considerable attention in recent years. While existing machine learning (ML)-based approaches have achieved notable progress, they predominantly focus on generating optimal layouts in a single attempt, often producing solutions that require subsequent refinement. To address this limitation, we propose RollPlace, a novel and generalized macro placement framework. RollPlace adopts a two-stage optimization strategy: generating initial placement solutions via ML methods or heuristic-based strategies, and refining these layouts efficiently by adjusting specific macros derived from the initial stage. This strategy circumvents the sequential generation constraints inherent in traditional RL-based placement methods. Furthermore, RollPlace seamlessly integrates Monte Carlo tree search (MCTS) to balance exploration and exploitation, and employs a rollout mechanism for efficient local search. Extensive experiments on the ISPD 2005 benchmark demonstrate that RollPlace outperforms state-of-the-art methods. Additionally, end-to-end experimental results based on OpenROAD across 19 benchmarks show that RollPlace excels in multiple metrics. The proposed framework offers a robust and scalable solution for addressing the growing complexity of modern chip design challenges.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3155-3168"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}