IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"AGCB: Adaptive Garbage Collection for Enhancing Lifetime and Performance of Bit-Alterable Flash Memory","authors":"Laifu Zhang;Yuhui Deng;Peng Zhou;Shujie Pang;Zhaorui Wu;Lin Cui;Zhen Zhang","doi":"10.1109/TCAD.2025.3639395","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3639395","url":null,"abstract":"Bit-alterable flash-based solid-state drives (SSDs), offering page-level erase operation, allow individual flash pages in a block to be erased independently. The page-level erase operation alleviates the overhead of page migration during garbage collection (GC) and improves the SSD lifetime. However, when the number of invalid pages within a block exceeds a certain threshold, the latency of page-level GCs using page-level erase may exceed that of block-level GCs. In bit-alterable flash memory, existing GC strategies dynamically choose between page-level and block-level GCs based on their latency. This often fails to fully exploit the advantage of page-level GC in reducing write amplification under low-load conditions. To address this limitation, we propose an adaptive GC strategy called AGCB to dynamically adjust GC operations by the runtime workload of flash channels, thereby enhancing SSD performance and lifetime. Specifically, AGCB classifies flash channels as busy or idle by monitoring the depth of the transaction queue in cache. According to this classification, AGCB selectively applies page-level or block-level GC operations, aiming to minimize the impact of GCs on host I/O requests. Meanwhile, we introduce a staged victim block selection scheme to further improve GC efficiency and wear leveling. The experimental results unveil that compared with the existing schemes, AGCB reduces the number of GC operations, average response time, and blocked user requests by an average of 14.6%, 14.7%, and 17.3%, respectively.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3073-3085"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Folivora: Ultralow-Power Microprocessor Design With Nano-Electromechanical Relay and Nanotube Memory","authors":"Siyuan Lu;Yuanqing Cheng;Ying Wang;Rui Wang","doi":"10.1109/TCAD.2025.3630558","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3630558","url":null,"abstract":"In the post-Moore era, CMOS technology scaling has encountered enormous design and fabrication challenges. “Power Wall” limits the further increase of integration density. Emerging AI computing and data center deployments aggravate the power consumption problem further. In the pursuit of an efficient computing paradigm, nano-electromechanical (NEM) relay and nanotube random access memory (NRAM) technology have attracted enormous attention and have ultralow-power consumption compared with CMOS counterparts. NEM relay is a kind of device based on electronic and mechanical interaction switching, characterized by remarkably low power consumption. This article explores the application of NEM relay and NRAM technology to build a complex RISC processor, aiming to achieve much lower power without degrading performance. The controller and data path can be implemented with primitive logic gates made of NEM relays, and the on-chip cache can be implemented with NRAM. Experimental results show that the energy efficiency of the processor design based on NEM relay and NRAM can be improved by 88.2% and 78.9% compared with CMOS technology-based in-order and out-of-order microprocessors, respectively. Meanwhile, the performance can be improved by 42.9% and the instruction execution time can be reduced by more than 17.9%, which implies the potential of NEM relay and NRAM for emerging ultralow-power applications.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3100-3112"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HAOT: Heterogeneous Hardware-Aware Tensor Computation Optimization Framework via Transformer","authors":"Zhipeng Wu;Han Wang;Ning Li;Heng Cao;Yu Liu","doi":"10.1109/TCAD.2025.3629566","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3629566","url":null,"abstract":"Efficient execution of tensor computations on different hardware, such as CPUs, GPUs, and spatial accelerators, poses substantial challenges due to divergent memory hierarchies, compute models, and architectural constraints. However, existing auto-tuning approaches typically fail to integrate hardware-aware formulations, leading to inefficient search processes and suboptimal utilization of hardware resources. To address these challenges, we introduce HAOT, a novel hardware-aware framework for optimizing tensor omputation that combines a learning-based scheduling policy with a hardware analytical model. Unlike traditional methods, HAOT not only adapts the learning-based scheduling strategy but also dynamically constrains the search space based on the availability of hardware resources, ensuring both the feasibility and optimal use of resources. Experiments across a range of hardware platforms show that HAOT achieves up to <inline-formula> <tex-math>$1.4times $ </tex-math></inline-formula> average speedup on individual tensor operations and a <inline-formula> <tex-math>$1.8times $ </tex-math></inline-formula> improvement in end-to-end deep learning workloads, outperforming state-of-the-art baselines. Ablation studies demonstrate the complementary roles of the Transformer-based policy model and the hardware analysis model, each contributing to generating high-quality schedule decisions. Furthermore, HAOT exhibits superior sample efficiency, requiring significantly fewer search trials to converge to the optimal schedule.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3129-3142"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Markov-Chain-Based PUF Using Chain-Block-Obfuscation Mechanism Resisting Machine Learning Attacks With High Uniformity Robustness","authors":"Junhong Gan;Hanqing Luo;Yuanfeng Xie;Liping Liang","doi":"10.1109/TCAD.2025.3634218","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3634218","url":null,"abstract":"Physical unclonable functions (PUFs) are lightweight hardware security primitives suitable for resource-constrained Internet of Things (IoT) devices. The arbiter PUF (APUF), as a classic strong PUF structure, is well-suited for lightweight device authentication. Unfortunately, due to certain structural characteristics, the classic APUF can be successfully modeled by various machine learning (ML) models with only a small number of challenge-response pair (CRP) samples. To address this security issue, in this article, we build upon the classic APUF structure by introducing a chain block obfuscation (CBO) mechanism and a Markov obfuscation mechanism at the input and output stages, respectively. This approach demonstrates strong resistance against four ML models—logistic regression (LR), support vector machine (SVM), covariance matrix adaptation evolutionary strategies (CMA-ES), and artificial neural networks (ANNs)—while optimizing hardware resource usage by at least 53.4% compared to previous attack-resistant structures. Even with up to 2M CRPs for training, the prediction accuracy remains around 50%. Additionally, <sc>xor</small>, a widely adopted output obfuscation mechanism by many researchers, has limitations in output uniformity when the number of intrachip parallel APUFs is small. Studies have shown that the uniqueness between intrachip APUFs may not reach the ideal value of 50%. In such cases, especially when there are only two parallel APUFs in the circuit, the uniformity of the <sc>xor</small> output is affected by insufficient uniqueness. To address this issue, this article proposes a MUX-based Markov output obfuscation mechanism. Experimental data on the Xilinx Artix-7 field-programmable gate array (FPGA) platform demonstrate that this mechanism exhibits strong robustness in uniformity compared to the traditional <sc>xor</small> output obfuscation, particularly when the number of intrachip parallel APUFs is small.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3526-3539"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lyapunov-Based Microgrid Optimization Scheduling Method","authors":"Hongning Li;Zihao Yan;Tuan Wang;Qingqi Pei","doi":"10.1109/TCAD.2025.3637550","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3637550","url":null,"abstract":"To address the issue of spatiotemporal coupling in random charging loads caused by the large-scale integration of electric vehicles (EVs), which disrupts the dynamic stability of microgrids, a Lyapunov-based microgrid optimization scheduling method (LOSM) is proposed. The key innovation lies in its dual virtual queue system, which meticulously models the spatiotemporally coupled randomness of BSS operation without relying on any forecasting, setting it apart from traditional prediction-dependent approaches. First, an energy storage system (ESS) model incorporating a dynamic energy management mechanism is established. In contrast to traditional forecasting-dependent methods, our approach introduces a virtual queue for the battery unit state of charge (SOC), which enables real-time adaptability and significantly reduces reliance on prediction accuracy. This mechanism accurately characterizes the time-varying charging and discharging processes, thereby mitigating the impact of power fluctuations caused by charging on system frequency stability. Subsequently, a spatiotemporally correlated virtual queue is constructed for the multimodal operation of the battery-swapping station (BSS), further enhancing real-time tracking capability without requiring high-accuracy forecasts. This achieves multidimensional and precise tracking of its electrical energy state. By integrating these virtual queues with a penalty factor adjustment mechanism, the proposed method simultaneously optimizes operational economy and dynamic stability while satisfying system stability constraints. Simulation analysis under a typical diurnal residential load profile with a 50-EV BSS and a significant penetration of wind and photovoltaic generation demonstrates that the proposed approach increases the revenue of the BSS by 5.67% and reduces the start-stop frequency of the diesel generator by 37.04%. This study provides a theoretical foundation for the robust operation of microgrids in scenarios involving EV integration and serves as an important reference for establishing dynamic stability assurance mechanisms in new power systems.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3428-3440"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring Deep-to-Shallow Transformable Neural Networks for Intelligent Embedded Systems","authors":"Xiangzhong Luo;Weichen Liu","doi":"10.1109/TCAD.2025.3632782","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3632782","url":null,"abstract":"Thanks to the evolving network depth, convolutional neural networks (CNNs) have achieved remarkable success across various embedded scenarios, paving the way for ubiquitous embedded intelligence. Despite its promise, the evolving network depth comes at the cost of degraded hardware efficiency. In contrast to deep networks, shallow networks can deliver superior hardware efficiency but often suffer from inferior accuracy. To address this dilemma, we propose double-win neural architecture search (DW-NAS), a novel deep-to-shallow transformable neural architecture search (NAS) paradigm tailored for resource-constrained intelligent embedded systems. In particular, DW-NAS strives to automatically explore deep networks to first win strong accuracy, which are then equivalently transformed into their shallow counterparts to further win strong hardware efficiency. In addition to search, we also propose two enhanced training techniques, including hybrid transformable training toward better training accuracy and arbitrary-resolution elastic training toward enabling natural network elasticity across arbitrary input resolutions. Extensive experimental results on two popular intelligent embedded systems (i.e., NVIDIA Jetson AGX Xavier and NVIDIA Jetson Nano) and two representative large-scale datasets (i.e., ImageNet and ImageNet-100) clearly demonstrate the superiority of DW-NAS over previous state-of-the-art (SOTA) NAS approaches.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3469-3483"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Signal-Path Recognition Approach to Multistage Op-Amp Pole-Zero Extraction With Applications","authors":"Mingzhen Li;Guoyong Shi","doi":"10.1109/TCAD.2025.3638265","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3638265","url":null,"abstract":"In the design of multistage operational amplifiers (Op-Amps), pole-zero (PZ) analysis lies at the core of whole design innovation for compensation. This article proposes a signal-path recognition method to help with the auto-generation of readable analytical PZ expressions from a circuit netlist. Prior symbolic PZ extraction methods have limitations in either requiring numerical references or yielding insufficiently compactness after simplification. The proposed method circumvents these limitations via a two-phase process: a topology simplification phase and a term simplification phase. In the topology simplification phase, signal paths of a multistage Op-Amp are detected via programmable routines, capturing the main amplification stages and frequency compensation paths, based on which the transfer function (TF) and PZs can be generated. In the term simplification phase, we propose a method that only refers to the magnitude orders of terms by assuming elementary device parameter orders based on a technology file. Sixteen test cases featuring varied compensation strategies are employed to demonstrate the applicability of this research. Our implementation delivers a fully automated netlist-to-PZ workflow, which can generate informative PZ expressions in compact and readable forms within minutes, offering useful insights to the circuit designer.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3045-3058"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy-Efficient In-Memory Vector Similarity Search With Fidelity-Aware Range Encoding","authors":"Chi-Tse Huang;Hsiang-Yun Cheng;An-Yeu Wu","doi":"10.1109/TCAD.2025.3631741","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3631741","url":null,"abstract":"Vector similarity search (VSS) is a crucial operation in applications of machine learning, but it often incurs high energy consumption due to frequent memory accesses. Previous works have adopted ternary content-addressable memories (TCAMs) to perform parallel VSS within memory. Among these approaches, exact-match TCAM (EX-TCAM) combined with range encoding has shown promise for executing in-memory VSS under the <inline-formula> <tex-math>$L_{infty } $ </tex-math></inline-formula> norm distance. Existing EX-TCAM-based approaches initiate the search from the positions of query vectors and iteratively expand the search ranges to identify the closest stored vectors. However, this initialization strategy leads to excessive search iterations and long codewords. To address these challenges, we present FORE, an EX-TCAM-based framework that significantly improves latency, energy efficiency, and accuracy for in-memory VSS. To reduce redundant search iterations, we first initialize the search from ranges based on the <inline-formula> <tex-math>$L_{infty } $ </tex-math></inline-formula> norm distance. To shorten the codeword length (CL), we then develop a range encoding scheme that supports range-to-range matching. In addition, we introduce a novel metric, “range fidelity (RF),” to evaluate the quality of range encoding. Building on the insight that a certain degree of loss in RF is tolerable in EX-TCAM-based VSS, we further propose a lossy range encoding scheme that yields more compact codewords without significantly compromising accuracy. Finally, FORE incorporates an <inline-formula> <tex-math>$L_{infty } $ </tex-math></inline-formula> norm distance-based training mechanism that further reduces search iterations and enhances classification accuracy in EX-TCAM-based VSS. Experimental results demonstrate that FORE improves energy efficiency by <inline-formula> <tex-math>$45.25times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$59.72times $ </tex-math></inline-formula> and reduces latency by <inline-formula> <tex-math>$4.47times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$5.66times $ </tex-math></inline-formula> compared with previous EX-TCAM-based methods within 1% accuracy loss. Moreover, FORE outperforms best-match TCAM (Best-TCAM)-based approaches by <inline-formula> <tex-math>$6.9times $ </tex-math></inline-formula> in energy efficiency under nonideal conditions.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3086-3099"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information","authors":"","doi":"10.1109/TCAD.2026.3700376","DOIUrl":"https://doi.org/10.1109/TCAD.2026.3700376","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"C3-C3"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11573029","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Espresso: Exploiting the Sparsity Property in Brain-Inspired Vision Sensors With Spatiotemporal Ordering","authors":"Leshan Li;Hongyi Li;Qingyuan Yang;Taoyi Wang;Yihan Lin;Mingtao Ou;Rong Zhao;Xinglong Ji","doi":"10.1109/TCAD.2025.3638266","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3638266","url":null,"abstract":"Brain-inspired vision sensors (BVSs), drawing inspiration from the human visual system, produce sparse, high-temporal-resolution data stream capable of capturing rapid object motion. However, real-time processing of such data while preserving its inherent sparsity presents a critical challenge for practical deployment. A key challenge is to leverage the spatiotemporal correlations among event stream (ES). Overlooking these correlations leads to prohibitively high query costs that even negate the benefits of sparsity while exploiting them introduces complications such as input–output order conflicts and tradeoffs between memory usage and latency. To address this, we present Espresso, an efficient hardware architecture that leverages the spatiotemporal order of events while explicitly preserving sparsity, achieving low-latency stream processing of event data. We first formalize a spatiotemporal order representation that identifies key features for stream processing on sparse events. Building on this, Espresso decouples the output window address from the input event address, resolving order conflicts via a dedicated queue mechanism and minimizing memory overhead through an optimized hash table. This enables immediate window-wise processing with minimal latency. To coordinate the pipeline, we design the Event-Scheduler, a streamlined finite state machine (FSM) that prunes computations on zero values and aligns input–output stream order discrepancies. Integrated together, these modules deliver scalable, high-throughput processing for event-driven vision tasks. Espresso achieves up to 5000 frames/s, offering a <inline-formula> <tex-math>$5.1times $ </tex-math></inline-formula> performance improvement over embedded GPUs. With parallel instantiations, it exceeds over 7000 frames/s in structured scenes and maintains over 2000 frames/s under complex-environment scenarios with minimal hardware overhead. These results establish Espresso as an efficient and scalable solution for real-time event-based vision processing, demonstrating the importance of spatiotemporal ordering in unlocking the full potential of BVSs.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3484-3497"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}