IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献_第2页

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information 集成电路与系统计算机辅助设计学报

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2025-01-21 DOI: 10.1109/TCAD.2024.3525199

引用次数: 0

SPLIM: Bridging the Gap Between Unstructured SpGEMM and Structured In-Situ Computing SPLIM：弥合非结构化SpGEMM和结构化原位计算之间的差距

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-25 DOI: 10.1109/TCAD.2024.3522882

Huize Li;Dan Chen;Tulika Mitra

{"title":"SPLIM: Bridging the Gap Between Unstructured SpGEMM and Structured In-Situ Computing","authors":"Huize Li;Dan Chen;Tulika Mitra","doi":"10.1109/TCAD.2024.3522882","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3522882","url":null,"abstract":"Sparse matrix-matrix multiplication (SpGEMM) is a critical kernel widely employed in machine learning and graph algorithms. However, high sparsity of real-world matrices makes SpGEMM memory-intensive. In-situ computing offers the potential to accelerate memory-intensive applications through high bandwidth and parallelism. Nevertheless, the irregular distribution of nonzeros renders software SpGEMM computation unstructured. In contrast, in-situ hardware platforms follow a fixed computation pattern, making them structured. The mismatch between unstructured software and structured hardware leads to suboptimal performance of current solutions. In this article, we propose SPLIM, a novel in-situ computing SpGEMM accelerator. SPLIM involves two innovations. First, we present a novel computation paradigm that converts SpGEMM into structured in-situ multiplication and unstructured accumulation. Second, we develop a unique coordinates alignment method utilizing in-situ search operations, effectively transforming unstructured accumulation into highly parallel search operations. Our experimental results demonstrate that SPLIM achieves <inline-formula> <tex-math>$276times $ </tex-math></inline-formula> performance improvement and <inline-formula> <tex-math>$687times $ </tex-math></inline-formula> energy saving compared to NVIDIA RTX A6000 GPU.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2412-2423"},"PeriodicalIF":2.7,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144100060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information 集成电路与系统计算机辅助设计学报

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-24 DOI: 10.1109/TCAD.2024.3513474

引用次数: 0

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information IEEE集成电路与系统计算机辅助设计汇刊

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-24 DOI: 10.1109/TCAD.2024.3513476

引用次数: 0

iSAFE: Enabling Evenness of Data Freshness in Multipriority Networked Intermittent Systems iSAFE：在多优先级网络间歇系统中实现数据新鲜度的均匀性

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-23 DOI: 10.1109/TCAD.2024.3522211

Wen Sheng Lim;Yu-Cheng Chen;Yu-Hsuan Chu;Chia-Heng Tu;Yuan-Hao Chang

{"title":"iSAFE: Enabling Evenness of Data Freshness in Multipriority Networked Intermittent Systems","authors":"Wen Sheng Lim;Yu-Cheng Chen;Yu-Hsuan Chu;Chia-Heng Tu;Yuan-Hao Chang","doi":"10.1109/TCAD.2024.3522211","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3522211","url":null,"abstract":"Environmental monitoring applications use energy harvesting to cover wide-range deployment, where devices are powered by ambient energy and operate intermittently when energy is sufficient. In such an intermittent networked system (NIS), a sink node is used to forward the environmental data collected by sensors to a central controller to reflect the physical environment status. Nevertheless, existing data forwarding algorithms for NISs cannot fulfill modern application requirements, where multiple types of data with different timeliness requirements (i.e., multipriorities) are desired to report real-time environmental data for monitoring critical situations. Without considering the multipriorities, we show in this article that it introduces a new problem: unevenness of data freshness. We then propose the sink node-based evenness-aware update forwarding (iSAFE) algorithm to provide evenness among different priorities of data sources in NISs. iSAFE consists of three important components: 1) a theoretical analysis to derive the optimal data forwarding interval between two adjacent status updates from the sensor; 2) an evenness-aware forwarding algorithm to adaptively adjust the forwarding interval based on the runtime status; and 3) a fresh-aware energy preservation algorithm to maintain the freshness of collected data. The experimental results show that iSAFE can achieve up to 682% evenness (94.47% close to the ideal) and 53.3% data freshness compared to the state of the art while being energy-efficient and scalable, suitable for modern applications.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2093-2104"},"PeriodicalIF":2.7,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144108346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Equivalent Thermal Conductance Network (ETCN) Model for Domain Decomposition and Efficient Thermal Simulation of GaN HEMTs GaN hemt的等效热导网络（ETCN）模型的区域分解和高效热模拟

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-23 DOI: 10.1109/TCAD.2024.3521324

Shunxiang Lan;Min Tang

{"title":"Equivalent Thermal Conductance Network (ETCN) Model for Domain Decomposition and Efficient Thermal Simulation of GaN HEMTs","authors":"Shunxiang Lan;Min Tang","doi":"10.1109/TCAD.2024.3521324","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3521324","url":null,"abstract":"Accurate and efficient simulation is essential for the thermal management of gallium nitride (GaN) high-electron-mobility transistors (HEMTs). However, conventional numerical approaches are usually time-consuming when dealing with transient thermal simulations with temperature-dependent parameters. To conquer this problem, we present a novel method based on the equivalent thermal conductance network (ETCN) model for efficient thermal simulation of GaN HEMTs. First, according to the temperature-dependent characteristics of the materials of the device, the entire structure is divided into region of variation (ROV) and region of fixity (ROF). Then, we decompose the transient response of ROF into a zero-input (ZI) and a zero-state (ZS) response based on the intrinsic property of linear time-invariant systems. After that, a novel ETCN model is developed for efficient transient simulation of GaN HEMTs. The principle of the ETCN model is to transform the impacts of the ROF on the ROV in the form of the equivalent thermal boundary conditions. By this means, we only need to focus on the ROV in the nonlinear iteration, enabling a significant reduction of degrees of freedom in solving the nonlinear equation and thus significantly improving the computational efficiency. In addition, the ETCN model is also available to handle the steady-state thermal problems. Several numerical examples are provided to validate the accuracy and efficiency of the proposed method. Compared with the conventional finite volume method, a speed-up of 105x is achieved by the ETCN model in simulating a typical multifinger GaN HEMT with microchannel cooling.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2343-2352"},"PeriodicalIF":2.7,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144100030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction 基于卷积和变压器层的双多模态融合VLSI拥塞预测

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-23 DOI: 10.1109/TCAD.2024.3522199

Hao Gu;Youwen Wang;Xinglin Zheng;Keyu Peng;Ziran Zhu;Jianli Chen;Jun Yang

{"title":"Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction","authors":"Hao Gu;Youwen Wang;Xinglin Zheng;Keyu Peng;Ziran Zhu;Jianli Chen;Jun Yang","doi":"10.1109/TCAD.2024.3522199","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3522199","url":null,"abstract":"In very large scale integration (VLSI) circuit physical design, precise congestion prediction during placement is crucial for enhancing routability and accelerating design processes. Existing congestion prediction models often encounter challenges in handling multimodal information and lack effective fusion of placement and netlist features, limiting their prediction accuracy. In this article, we present a novel congestion prediction model that leverages dual multimodal fusions with convolution and transformer layers to effectively capture the multiscale placement information and enhance congestion prediction accuracy. We first adopt convolutional neural networks (CNNs) to extract grid-based placement features and heterogeneous graph convolutional networks (HGCNs) to extract netlist information. To help the model understand the correlation between different modalities, we then propose an early feature fusion (EFF) to integrate netlist knowledge into multiscale placement features at multimodal interaction subspace. Besides, a deep feature fusion (DFF) method is proposed to further fuse multimodal features, which has multiple vision transformer layers based on adaptive attention enhancement technology. These layers include self-attention (SA) to boost intramodal features and cross-attention (CA) to perform cross-modal feature fusion on netlist and grid-based placement features. Finally, the output features of DFF are sent into the cascaded decoder to recover the congestion map by exploiting several upsampling layers and merging with EFF features. Compared with the existing state-of-the-art congestion prediction models, experimental results demonstrate that our model not only outperforms them in prediction accuracy, but also excels in reducing routing congestion when integrated into the placer DREAMPlace.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2378-2391"},"PeriodicalIF":2.7,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144099947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning 通过非理想PIM器件微调提高MLC PIM的深度神经网络精度

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-23 DOI: 10.1109/TCAD.2024.3521195

Hao Lv;Lei Zhang;Ying Wang

{"title":"Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning","authors":"Hao Lv;Lei Zhang;Ying Wang","doi":"10.1109/TCAD.2024.3521195","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3521195","url":null,"abstract":"Resistive random access memory (RRAM) emerges as a promising technology for developing energy-efficient deep neural network (DNN) accelerators, owing to its analog computing paradigm for matrix-vector multiplication. However, the inherent nonideal device features of RRAM cells, such as device variation, read disturbances, and limited on/off ratio, present challenges for model deployment. Therefore, to ensure accurate storage and computing precision for RRAM-based accelerators, a widely used practice is encoding a DNN weight by multiple cells, resulting in significant memory overhead and underutilization. This challenge is further exacerbated by the rapid increases in model size witnessed in recent years. While the one-to-one weight-cell mapping strategy can improve memory utilization, it inevitably introduces deviations in the mapped DNN weight from the desired value due to RRAM variation issues, leading to model accuracy degradation. In response to this challenge, we abstract the model optimization on RRAM chips as a non-ideal PIM device optimization problem, aimed at optimizing model accuracy without the requirement of precise weight programming. We systematically analyze the model optimization behavior on multilevel RRAM devices by investigating the accuracy recovery process of various fine-tuning strategies in recovering model performance under the non-ideal PIM device setting. Based on the analysis, we propose a non-ideal PIM device finetune scheme to recover the model performance for multilevel RRAM under the non-ideal PIM device setting. Our proposed scheme leverages knowledge distillation and exploits input/output information of the model on RRAM to guide the fine-tuning process, finally restoring its accuracy. Experimental results demonstrate the efficacy of our non-ideal PIM device fine-tuning scheme, achieving nearly complete recovery of model performance. Our approach yields over a 3% improvement in model accuracy compared to variation-aware training approaches.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2277-2286"},"PeriodicalIF":2.7,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144108223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HTs-GCN: Identifying Hardware Trojan Nodes in Integrated Circuits Using a Graph Convolutional Network 利用图卷积网络识别集成电路中的硬件木马节点

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-19 DOI: 10.1109/TCAD.2024.3520522

Jie Xiao;Shuiliang Chai;Yanjiao Gao;Yuhao Huang;Fan Zhang;Tieming Chen

{"title":"HTs-GCN: Identifying Hardware Trojan Nodes in Integrated Circuits Using a Graph Convolutional Network","authors":"Jie Xiao;Shuiliang Chai;Yanjiao Gao;Yuhao Huang;Fan Zhang;Tieming Chen","doi":"10.1109/TCAD.2024.3520522","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3520522","url":null,"abstract":"Hardware Trojans (HTs) present significant security threats to integrated circuits. Detecting and locating HTs is crucial for mitigating these threats. Thus, this article proposes a method called HTs-GCN, which utilizes a graph convolutional network (GCN) to identify HTs. First, it extracts two novel features of gate nodes using a depth-first search strategy and topological logical analysis to enrich the feature information of circuit nodes. Second, through a message-passing mechanism, it designs a local feature aggregation method based on the GCN and a global feature fusion method based on an attention mechanism to improve the representation capability of circuit node features. Then, leveraging the concept of stochastic gradient descent and incorporating mini-batch oversampling and under-sampling techniques, it employs a dataset imbalance handling method to address the scarcity of HT nodes in circuits. These approaches significantly enhance the distinguishability between gate nodes with HTs and other gate nodes while reducing computational complexity. Experimental results indicate that HTs-GCN outperforms the recently proposed NHTD-GL method in terms of recall: it achieves approximately 7.8% points higher recall while maintaining similar accuracy. HTs-GCN demonstrates exceptional generalizability, with an average recall and accuracy of 93.0% and 100%, respectively, on infrequently used circuits in the Trust-Hub benchmark. In addition, on the TRIT-TC benchmark, HTs-GCN achieves excellent average true positive rate (TPR) and true negative rate (TNR) of 95.1% and 94.4%, respectively. Furthermore, HTs-GCN exhibits robust performance under gate modification attacks, with average TPR and TNR reaching 82.1% and 92.5%, respectively.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2353-2366"},"PeriodicalIF":2.7,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144100029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multiobjective Optimization for Common-Centroid Placement of Analog Transistors 模拟晶体管共质心布置的多目标优化

IF 2.7 3区计算机科学

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-12-19 DOI: 10.1109/TCAD.2024.3520521

Supriyo Maji;Hyungjoo Park;Gi-Moon Hong;Souradip Poddar;David Z. Pan

{"title":"Multiobjective Optimization for Common-Centroid Placement of Analog Transistors","authors":"Supriyo Maji;Hyungjoo Park;Gi-Moon Hong;Souradip Poddar;David Z. Pan","doi":"10.1109/TCAD.2024.3520521","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3520521","url":null,"abstract":"In analog circuits, process variation can cause unpredictability in circuit performance. Common-centroid (CC) type layouts have been shown to mitigate process-induced variations and are widely used to match circuit elements. Nevertheless, selecting the most suitable CC topology necessitates careful consideration of important layout constraints. Manual handling of these constraints becomes challenging, especially with large size problems. State-of-the-art CC placement methods lack an optimization framework to handle important layout constraints collectively. They also require manual efforts and consequently, the solutions can be suboptimal. To address this, we propose a unified framework based on multiobjective optimization for CC placement of analog transistors. Our method handles various constraints, including degree of dispersion, routing complexity, diffusion sharing, and layout dependent effects. The multiobjective optimization provides better handling of the objectives when compared to single-objective optimization. Moreover, compared to existing methods, our method explores more CC topologies. Post-layout simulation results show better performance compared to state-of-the-art techniques in generating CC layouts.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 6","pages":"2029-2039"},"PeriodicalIF":2.7,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144108232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0