IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems最新文献

{"title":"Key in the Pocket: Intelligent Key Recovery With Genetic Algorithm in Correlation-Enhanced Collision Attacks","authors":"Jiawei Zhang;Jiangshan Long;Changhai Ou;Kexin Qiao;Fan Zhang;Shi Yan;Debiao He","doi":"10.1109/TCAD.2025.3633629","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3633629","url":null,"abstract":"By introducing collision information, the existing side-channel correlation-enhanced collision attacks (CECAs) performed collision-chain detection, quickly filtered out candidates unsatisfying collision conditions, and extracted a part of optimal candidates for further processing, thereby rapidly and significantly reducing the key candidate space and the difficulty of key recovery. However, they are still limited by disadvantages such as serial implementation, complex parameter settings, and lack of intelligence, resulting in a low success rate (SR) of key recovery. To address these issues, we first present a collision detection framework with genetic algorithm (CDGA), which exploits genetic algorithm to detect the collision chains and has a strong capability of global searching. Second, we theoretically analyze the performance of CECA and bound the searching depth of its output candidate vectors with a confidence level using a data-driven hypothesis test that provides confidence bounds for Gaussian leakages and an approximation based on central limit theory (CLT) for non-Gaussian cases, which facilitates effective and stable population initialization. Third, benefiting from our hypothesis-test-guided design, we propose a goal-directed mutation that prioritizes promising collision candidates, thus improving efficiency and adaptability of the CDGA. Finally, to optimize the evolution of CDGA, we introduce a roulette selection strategy to employ a probability assignment based on individual fitness values to guarantee the preferential selection of superior genes. Comprehensive experiments on DPA Contest v4.1 [AES-256 with Rotated S-boxes Masking (RSM)] and an AT89S52 AES-128 platform demonstrate that CDGA achieves faster convergence and higher key-recovery SRs compared with TOC/FTC/FCC and Wiemers’ cumulative-correlation selection.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3498-3511"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BS-PDN-Last: Toward Optimal Power Delivery Network Design With Multifunctional Backside Metal Layers","authors":"Min Gyu Park;Sung Kyu Lim","doi":"10.1109/TCAD.2025.3631591","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3631591","url":null,"abstract":"Backside metal integration effectively mitigates IR-drop challenges, which become increasingly difficult to manage as CMOS technology scales down. However, compared to frontside-only chip designs, implementing backside metal incurs additional costs due to processes such as wafer thinning and nano-through silicon vias (nTSV) formulation. To maximize the advantages of backside integration, the industry is now exploring functional backside technology. This article introduces a novel backside power delivery network (BS-PDN)-last flow that is critical for the multifunctional utilization of backside metal layers. The BS-PDN-last flow defers power/ground (P/G) routing to a later stage of the physical design process, in contrast to the conventional approach where it is performed early in the flow. As a result, BS-PDN-last overcomes the voltage drop and performance tradeoffs inherent in conventional flows, enabling substantial performance gains while maintaining low IR-drop levels. Experimental results show that the BS-PDN-last flow achieves a 90% reduction in total negative slack (TNS) and a 12% performance gain with backside clock delivery network (BS-CDN).","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3211-3223"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resource-Optimized Time-Multiplexed Constant Multiplication via Adjacency Matrix Modeling","authors":"Hao Sun;Martin Kumm;Liansheng Liu;Zhixian Zhang;Yu Peng","doi":"10.1109/TCAD.2025.3632193","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3632193","url":null,"abstract":"This article presents TmCM-AM, a new time-multiplexed constant multiplication framework based on adjacency matrix modeling. The TmCM-AM framework provides a universal and efficient approach for digital signal processing applications using much fewer resources and with greater adaptability based on conventional methods. By transforming adder graphs into adjacency matrices and using an optimization algorithm, the proposed framework minimizes the number of required adders and multiplexers to a large degree. In particular, three mathematical properties of adjacency matrices based on properties of adder graphs are presented. Meanwhile, the adjacency matrix is used to model time-multiplexed adder graphs in detail, making hardware architecture analysis possible through matrix computation. Finally, heuristic algorithms are used to generate the best possible solution from matrices calculated. Experimental verification through FPGA and ASIC implementations further confirms the feasibility of TmCM-AM, presenting enormous reductions in area and power dissipation, as well as delay metrics across random data and various real-life coefficient sets.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3305-3318"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LORA: A Latency-Oriented Recurrent Architecture for Large Language Model on Multi-FPGA Platform With Communication Optimization","authors":"Zhendong Zheng;Qianyu Cheng;Teng Wang;Wenqi Lou;Lei Gong;Xianglan Chen;Chao Wang;Xuehai Zhou","doi":"10.1109/TCAD.2025.3629537","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3629537","url":null,"abstract":"The remarkable performance of large language models (LLMs) has driven their widespread deployment in data centers to support diverse user-facing applications. However, the rapidly growing computational and storage demands of these models have made single-device deployment increasingly impractical. Prior research on LLM inference has primarily addressed this challenge through algorithmic optimizations such as quantization or by integrating customized hardware acceleration frameworks. As model parameters continue to scale, multidevice deployment has become a necessary approach for enabling efficient LLM inference. Nevertheless, constructing low-latency multidevice platforms for LLMs inference using available field-programmable gate array (FPGA) or GPU accelerators remains constrained by inefficient synchronization schemes or limited compute intensity in current architectures. Furthermore, existing solutions often lack co-optimized designs that effectively integrate communication with computation. To address these limitations, this article proposes latency-oriented recurrent architecture (LORA), a low-latency end-to-end LLMs acceleration platform utilizing multiple FPGAs. First, we optimize the synchronization timing within the LLMs to minimize storage, computation, and block random-access memory (BRAM) overhead. Second, we tightly couple communication and computation through techniques such as pipeline overlapping and input data packing. Next, we deploy homogeneous accelerators on each FPGA device, leveraging a recurrent architecture to further reduce inference latency. Finally, we apply FPGA-specific optimizations and conduct performance modeling and analysis of the acceleration framework to select optimal deployment parameters for various computational tasks. Implemented on Xilinx Alveo U280 FPGAs, LORA-F and LORA-Q achieve average speedups of <inline-formula> <tex-math>$14.4times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$32.6times $ </tex-math></inline-formula>, respectively, compared with NVIDIA V100 GPUs when running modern LLMs. Compared with existing multi-FPGA accelerator platforms, LORA-F and LORA-Q demonstrate average performance improvements of up to <inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$4.3times $ </tex-math></inline-formula>, respectively.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3319-3332"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication","authors":"Yicheng Huang;Xueyan Wang;Shicheng Ma;Song Bian;Meng Li;Gang Qu","doi":"10.1109/TCAD.2025.3634196","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3634196","url":null,"abstract":"Fully homomorphic encryption (FHE) allows operations to be performed directly on encrypted data, and has attracted massive attention in data security scenarios. Numerous resource-efficient FHE acceleration methods have been proposed, including many on the optimization of modular multiplication (MM), a fundamental operation in FHE, by leveraging Karatsuba multiplication and number-theoretic transform (NTT)-friendly moduli for montgomery MM (MMM). However, FHE is not yet practical due to its significant resource overheads. In this article, we report an automated Karatsuba decomposition search strategy that drastically improves the efficiency of MM implementation. Our key idea is to integrate NTT-friendly moduli into Karatsuba decomposition within parallel MMM, and incorporate optimization features such as truncated multiplication <inline-formula> <tex-math>$lfloor AB/Rrfloor $ </tex-math></inline-formula> and MM AB mod R. After a careful analysis of the optimization space, we propose an automated Karatsuba decomposition optimization search algorithm based on a greedy strategy to enhance efficiency and effectiveness. Theoretical analysis shows that, under the mainstream NTT-friendly modulus conditions, the optimized two, three, and four-term Karatsuba decomposition schemes achieve an average area reduction of 18% for MMM over the basic Karatsuba method and 57% over the classical Schoolbook method. Furthermore, hardware implementations on FPGA demonstrate 29%–79% improvement, with an average of 59%, in area/throughput compared to the state-of-the-art implementations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3512-3525"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TC-Cache: Accelerating Restore Performance With Type-Aware Cooperative Cache in Erasure-Coded Deduplicated Storage Systems","authors":"Chunxue Zuo;Fang Wang;Jun Liu;Li Liu","doi":"10.1109/TCAD.2025.3629538","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3629538","url":null,"abstract":"To ensure reliability, modern deduplication-based storage systems exploit erasure coding to redundantly distribute objects that store post-deduplicated data across multiple storage nodes. In the case of node failures, the failure recovery of impacted objects performs degraded read operations by reading from these storage nodes. However, this degraded read scheme introduces the additional available objects into the restore cache, which poses challenges to state-of-the-art caching policies applied in erasure-coded deduplicated storage systems. On one hand, chunk-based caching method fails to cache the remaining available objects after the unavailable objects are rebuilt, resulting in multiple reads of accessed objects and severely degrading restore performance. On the other hand, object-based caching methods do not identify lost objects to which duplicate chunks belong, causing unused objects to unnecessarily occupy cache space and destroy cache locality. In this article, we propose type-aware cooperative cache (TC-Cache), a restore cache scheme for node failures, which combines object-based caching and chunk-based caching methods to improve restore performance. The main idea of TC-Cache is to identify objects to which redundant data belongs, and selectively handle degraded reads of two types of objects in caches of different granularities during failure recovery to enhance cache utilization and maintain cache locality. Extensive experiments based on three real-world datasets demonstrate that TC-Cache outperforms state-of-the-art cache algorithms in terms of restore performance by 21%–65% with low computing overhead.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3415-3427"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector","authors":"Yihang Qiu;Zengrong Huang;Simin Tao;Hongda Zhang;Weiguo Li;Xinhua Lai;Rui Wang;Weiqiang Wang;Xingquan Li","doi":"10.1109/TCAD.2025.3632188","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3632188","url":null,"abstract":"Recent research has demonstrated that artificial intelligence (AI) can assist electronic design automation (EDA) in improving both the quality and efficiency of chip design. But current AI for EDA (AI-EDA) infrastructures remain fragmented, lacking comprehensive solutions for the entire data pipeline from design execution to AI integration. Key challenges include fragmented flow engines that generate raw data, heterogeneous file formats for data exchange, nonstandardized data extraction methods, and poorly organized data storage. This work introduces a unified open-source library for EDA (AiEDA) that addresses these issues. AiEDA integrates multiple design-to-vector data representation techniques that transform diverse chip design data into universal multilevel vector representations, establishing an AI-aided design (AAD) paradigm optimized for AI-EDA workflows. AiEDA provides complete physical design flows with programmatic data extraction and standardized Python interfaces that bridge EDA datasets and AI frameworks. Leveraging the AiEDA library, we generate iDATA, a 600-GB dataset of structured data derived from 50 real chip designs (28 nm), and validate its effectiveness through five representative AAD tasks spanning prediction, generation, and optimization. The code of AiEDA is publicly available at <uri>https://github.com/OSCC-Project/AiEDA</uri>, providing a foundation for future AI-EDA research.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3374-3387"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation","authors":"Zhaorui Chen;Liao Huang;Xiao Xiong;Dajiang Liu","doi":"10.1109/TCAD.2025.3630548","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3630548","url":null,"abstract":"Coarse-grained reconfigurable arrays (CGRAs) play an important role in accelerating computation-intensive applications due to their flexibility and power efficiency. Most existing mapping works for CGRAs assume that all the data of a loop kernel can be previously moved from DRAM to scratchpad memory (SPM) with one data transfer. However, when targeting low-power CGRAs, the SPM can hardly hold the entire data, even for a small loop kernel, and it inevitably incurs multiple data transfers, leading to notable costs. In this case, where and how to perform data transfer, considering the DRAM access behavior, is crucial to the overall execution performance. To this end, this article proposes a data transfer optimization method to simultaneously optimize loop pipelining and data transfer. Since there is an interplay between loop structure and data transfer, we establish an optimization problem considering both polyhedral transformation and transfer strategy exploration, offering opportunities to find the near-optimal data transfer strategy within the search space. The experimental results show that compared with existing methods, our method can achieve <inline-formula> <tex-math>$1.36times -4.55times $ </tex-math></inline-formula> speedup for loop kernels with different on-chip buffer sizes and only increases the compilation time by a small amount.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3291-3304"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approximate Logic Synthesis Via Iterative SMT-Based Subcircuit Rewriting","authors":"Morteza Rezaalipour;Marco Biasion;Francesco Costa;Cristian Tirelli;Lorenzo Ferretti;Rodrigo Otoni;George A. Constantinides;Laura Pozzi","doi":"10.1109/TCAD.2025.3638267","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3638267","url":null,"abstract":"This article presents a novel iterative approach to achieve effective and efficient approximate logic synthesis (ALS). The core idea is to perform circuit rewriting in a way that is both local, i.e., is applied piecewise to selected subcircuits, and extensive, i.e., systematically explores the design space for good solutions. Concretely, we propose <sc>SubXPAT</small>, a new Boolean rewriting framework which iteratively uses satisfiability modulo theories (SMT) solving to select and approximate key parts of a circuit. Selection aims at finding subcircuits that at the same time include a significant number of gates and can be efficiently approximated, which is done by searching for large convex subcircuits with a limited number of inputs and outputs. Approximation is guided by the use of a parametric template, structured as a sum of products, which allows for fine-grained control over the subcircuit characteristics. SubXPAT was implemented as an open-source tool and compared against other ALS tools implementing state-of-the-art techniques. Our experimental evaluation used a broad range of arithmetic circuits with different bit-widths, and our results indicate that SubXPAT generates approximate circuits that are more area-efficient than those generated by state-of-the-art techniques in 72% of the cases.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3224-3237"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators","authors":"Minjin Tang;Mei Wen","doi":"10.1109/TCAD.2025.3639392","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3639392","url":null,"abstract":"Matrix operators are fundamental to various applications, particularly in deep learning. While early models relied on dense operations, techniques like pruning have introduced sparsity, leading to a mix of dense and sparse operator types. Most existing accelerators are specialized for specific operators and perform poorly in mixed scenarios, while those supporting multiple operators often lack flexibility and suffer from suboptimal performance. To overcome these limitations, we propose VersaAccel, a configurable accelerator for sparse and dense matrix operators. It supports four distinct configurations, each optimized for a set of operators. A key feature of our design is its adaptive configuration selection mechanism, driven by a lightweight cost model that explicitly evaluates the performance-energy tradeoff between available options. This allows VersaAccel to dynamically choose the most efficient configuration—opting for higher performance when the gain outweighs the energy cost, or prioritizing energy efficiency when appropriate. Experimental results demonstrate that VersaAccel achieves an average performance/area improvement of <inline-formula> <tex-math>$3.10times $ </tex-math></inline-formula> across multiple operators [matrix-vector multiplication (MV), matrix multiplication (MM), sparse MV (SpMV), sparse MM (SpMM), and sparse matrix-SpMM (SpMSpM)] and <inline-formula> <tex-math>$4.06times $ </tex-math></inline-formula> on full model evaluations (ResNet18, VGG16, LLaMA2-7B, and BERT-Base), compared to mainstream accelerators.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3059-3072"},"PeriodicalIF":3.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}